DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

LFE3-150EA-7LFN1156C 查看數據表(PDF) - Lattice Semiconductor

零件编号
产品描述 (功能)
生产厂家
LFE3-150EA-7LFN1156C
Lattice
Lattice Semiconductor Lattice
LFE3-150EA-7LFN1156C Datasheet PDF : 140 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
Architecture
LatticeECP3 Family Data Sheet
chain in order to better match the reference and feedback signals. This digital code from the ALU is also transmit-
ted via the Digital Control bus (DCNTL) bus to its associated Slave Delay lines (two per DLL). The ALUHOLD input
allows the user to suspend the ALU output at its current value. The UDDCNTL signal allows the user to latch the
current value on the DCNTL bus.
The DLL has two clock outputs, CLKOP and CLKOS. These outputs can individually select one of the outputs from
the tapped delay line. The CLKOS has optional fine delay shift and divider blocks to allow this output to be further
modified, if required. The fine delay shift block allows the CLKOS output to phase shifted a further 45, 22.5 or 11.25
degrees relative to its normal position. Both the CLKOS and CLKOP outputs are available with optional duty cycle
correction. Divide by two and divide by four frequencies are available at CLKOS. The LOCK output signal is
asserted when the DLL is locked. Figure 2-5 shows the DLL block diagram and Table 2-5 provides a description of
the DLL inputs and outputs.
The user can configure the DLL for many common functions such as time reference delay mode and clock injection
removal mode. Lattice provides primitives in its design tools for these functions.
Figure 2-5. Delay Locked Loop Diagram (DLL)
ALUHOLD
÷4
÷2
(from routing
or external pin)
CLKI
from CLKOP (DLL
internal), from clock net
(CLKOP) or from a user
clock (pin or logic)
CLKFB
UDDCNTL
RSTN
INCI
GRAYI[5:0]
Reference
Phase
Detector
Feedback
Arithmetic
Logic Unit
Delay Chain
Delay0
Delay1
Delay2
Delay3
Delay4
Duty
Cycle
50%
Output
Muxes
Duty
Cycle
50%
÷4
÷2
Lock
Detect
6
Digital
Control
Output
* This signal is not user accessible. This can only be used to feed the slave delay line.
CLKOP
CLKOS
LOCK
DCNTL[5:0]*
DIFF
INCO
GRAYO[5:0]
2-8

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]