LFE3-150EA-6MG328I 查看數據表（PDF） - Lattice Semiconductor
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LFE3-150EA-6MG328I Datasheet PDF : 140 Pages
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Figure 2-2. PFU Diagram
From
Routing
Architecture
LatticeECP3 Family Data Sheet
LUT4 &
CARRY
LUT4 &
CARRY
Slice 0
D
D
FF
FF
LUT4 &
CARRY
LUT4 &
CARRY
Slice 1
D
D
FF
FF
LUT4 &
CARRY
LUT4 &
CARRY
Slice 2
D
D
FF
FF
LUT4
LUT4
Slice 3
To
Routing
Slice
Slice 0 through Slice 2 contain two LUT4s feeding two registers, whereas Slice 3 contains two LUT4s only. For
PFUs, Slice 0 through Slice 2 can be configured as distributed memory, a capability not available in the PFF.
Table 2-1 shows the capability of the slices in both PFF and PFU blocks along with the operation modes they
enable. In addition, each PFU contains logic that allows the LUTs to be combined to perform functions such as
LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset functions (programmable as synchronous/
asynchronous), clock select, chip-select and wider RAM/ROM functions.
Table 2-1. Resources and Modes Available per Slice
Slice
Slice 0
Slice 1
Slice 2
Slice 3
PFU BLock
PFF Block
Resources
Modes
Resources
Modes
2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM
2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM
2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM
2 LUT4s
Logic, ROM
2 LUT4s
Logic, ROM
Figure 2-3 shows an overview of the internal logic of the slice. The registers in the slice can be configured for posi-
tive/negative and edge triggered or level sensitive clocks.
Slices 0, 1 and 2 have 14 input signals: 13 signals from routing and one from the carry-chain (from the adjacent
slice or PFU). There are seven outputs: six to routing and one to carry-chain (to the adjacent PFU). Slice 3 has 10
input signals from routing and four signals to routing. Table 2-2 lists the signals associated with Slice 0 to Slice 2.
2-3
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