LPC2388FBD144(2008) 查看數據表（PDF） - NXP Semiconductors.
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LPC2388FBD144
(Rev.:2008)
(Rev.:2008)
NXP Semiconductors.
LPC2388FBD144 Datasheet PDF : 61 Pages
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NXP Semiconductors
5. Block diagram
LPC2388
Single-chip 16-bit/32-bit microcontroller
P0, P1, P2,
P3, P4
RMII(8)
EINT3 to EINT0
P0, P2
2 × CAP0/CAP1/
CAP2/CAP3
4 × MAT2,
2 × MAT0/MAT1/
MAT3
6 × PWM1
2 × PCAP1
P0, P1
8 × AD0
AOUT
VBAT
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RTCX1
RTCX2
ALARM
TMS TDI trace signals
TRST TCK TDO
EXTIN0
XTAL1
XTAL2
VDDA
RESET
VDD(3V3)
LPC2388
64 kB
SRAM
512 kB
FLASH
TEST/DEBUG
INTERFACE
HIGH-SPEED
GPI/O
104 PINS
TOTAL
INTERNAL
CONTROLLERS
SRAM FLASH
ARM7TDMI-S
PLL
system
clock
SYSTEM
FUNCTIONS
INTERNAL RC
OSCILLATOR
VECTORED
INTERRUPT
CONTROLLER
EXTERNAL
MEMORY
CONTROLLER
AHB2
AHB
BRIDGE
AHB
BRIDGE
AHB1
ETHERNET
MAC WITH
DMA
16 kB
SRAM
MASTER AHB TO SLAVE
PORT AHB BRIDGE PORT
AHB TO
APB BRIDGE
16 kB
SRAM
USB WITH
4 kB RAM
AND DMA
GP DMA
CONTROLLER
EXTERNAL INTERRUPTS
CAPTURE/COMPARE
TIMER0/TIMER1/
TIMER2/TIMER3
I2S INTERFACE
PWM1
SPI, SSP0 INTERFACE
LEGACY GPI/O
56 PINS TOTAL
A/D CONVERTER
D/A CONVERTER
2 kB BATTERY RAM
RTC
OSCILLATOR
REAL-
TIME
CLOCK
WATCHDOG TIMER
SYSTEM CONTROL
SSP1 INTERFACE
SD/MMC CARD
INTERFACE
UART0, UART2, UART3
UART1
CAN1, CAN2
I2C0, I2C1, I2C2
VREF
VSSA, VSS
VDD(DCDC)(3V3)
D[7:0]
A[15:0]
OE, CS0, CS1,
BLS0
VBUS
USB port 1
USB port 2
I2SRX_CLK
I2STX_CLK
I2SRX_WS
I2STX_WS
I2SRX_SDA
I2STX_SDA
SCK, SCK0
MOSI, MOSI0
MISO, MISO0
SSEL, SSEL0
SCK1
MOSI1
MISO1
SSEL1
MCICLK, MCIPWR
MCICMD,
MCIDAT[3:0]
TXD0, TXD2, TXD3
RXD0, RXD2, RXD3
TXD1
RXD1
DTR1, RTS1
DSR1, CTS1, DCD1,
RI1
RD1, RD2
TD1, TD2
SCL0, SCL1, SCL2
SDA0, SDA1, SDA2
Fig 1. LPC2388 block diagram
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LPC2388_1
Product data sheet
Rev. 01 — 19 December 2008
© NXP B.V. 2008. All rights reserved.
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