VSC6110 查看數據表（PDF） - Vitesse Semiconductor

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VSC6110

Low Jitter Clock Multiplier and Distributor

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC6108/10/12

Low Jitter

Clock Multiplier and Distributor

Features

• Recommended Companion for VSC6250 500MHz

Deskew IC and Vitesse Timing Generator ICs

• Input Clock Frequency: 50MHz to 622MHz

• Output Clock Frequency: 100MHz to 1.25GHz

• 1 Differential ECL or PECL Clock Input

• 18 Differential ECL or PECL Clock Outputs

• Very Low Jitter: 4ps rms, 25ps Peak-to-Peak

• 10µs Lock Time

• < 50ps Skew Between Outputs

• Single Supply: 3.3V + 5% @ 2 Watts

• Commercial (0o to +70oC) Temperature Range

• Package: 10mm x 10mm 64 PQFP

General Description

The VSC6108/10/12 are a family of low-jitter clock multiplication and distribution ICs. Each IC uses a

phase locked-loop to lock an on-chip low-noise VCO to an off-chip reference frequency. The VCO output can

be divided down and is output to 18 differential ECL outputs. The VSC6108/10/12 are packaged in a 10 mm x

10 mm 64-pin plastic quad flat pack and consume less than 2 Watts from a single 3.3V power supply.

The VSC6108/10/12 provide high-precision clocks for ATE, instrumentation, telecommunications, data-

communications, and computer system applications where jitter and skew are critical timing parameters. Skew

between outputs is less than 50 ps. Jitter is less than 4 ps rms or 25 ps peak-to-peak. Lock time is 10 µs.

VSC6108/10/12 Functional Block Diagram

OUT0

OUT0N

OUT1

OUT1N

IN

INN

Phase

Detector

Loop

Filter

VCO

Bypass

2,4,8,16

FISEL1

FISEL0

FOSEL2

FOSEL1

FOSEL0

4,8,16,32

OUT17

OUT17N

G52224-0, Rev 2.1

2/15/99

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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