CXD8059Q 查看數據表（PDF） - Sony Semiconductor
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CXD8059Q Datasheet PDF : 3 Pages
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34
XY
33
MON
1
MD9
32
MD8
31
MD7
30
MD6
29
MD5
28
MD4
27
MD3
24
MD2
23
MD1
22
MD0
21
MDM1
20
MDM2
61
TST
8
ACLR
9
AINC
11
FCLR
12
FLOE
63
MSFI
64
STFI
49
OE
62
PAL
14
ADR
16
RCS
17
CS
19
CKD
18
CKX
56
48
AD10
47
AD9
46
AD8
45
AD7
44
AD6
43
AD5
41
AD4
40
AD3
39
AD2
38
AD1
37
AD0
36
ADM1
35
ADM2
52
TSTO 5
53
TSTO 4
54
TSTO 3
55
TSTO 2
59
TSTO 1
60
TSTO 0
51
MSFO
50
STFO
15
DIO
CXD8059Q(2/3)
INPUT
ACLR
; ADDRESS CLEAR TIMING PULSE
X MODE
HD INPUT (
)
Y MODE
VD INPUT (
)
ADR
; SERIAL ADDRESS
AINC
; ADDRESS INCREMENT TIMING PULSE
X MODE
HIGH OR LOW (FIXED)
Y MODE
HD INPUT (
)
CK
; SYSTEM CLOCK
CKD
; SERIAL INTERFACE CLOCK
CKX
; SWITCHING TIMING PULSE
CS
; CHIP SELECT (LOW : ACTIVE)
FCLR
; FIELD CLEAR TIMING PULSE (FOR PAL)
X MODE
FIELD RESET PULSE
Y MODE
HIGH OR LOW (FIXED)
FLOE
; FIELD ODD / EVEN PULSE
HIGH : EVEN FIELD
MD0 - MD9 ; 9.2 BIT DIGITAL MODULATION DATA IN
(2'S COMPLEMENT)
MDM1, MDM2 ; 9.2 BIT DIGITAL MODULATION DATA IN
(2'S COMPLEMENT)
MON
; MODULATION ON / OFF CONTROL
LOW : MODULATION ON
MSFI
; MULTI-SHIFT FLAG IN (LOW : ACTIVE)
Y MODE IC
PULL UP
X MODE IC
CONNECT MSFO OUT
OF Y MODE IC TO MSFI
OF X MODE IC
OE
; OUTPUT ENABLE
(LOW : ENABLE, HIGH : DISABLE)
PAL
; NTSC / PAL SELECT
RCS
; READ CHIP SELECT (LOW : ACTIVE)
STFI
; STREAM FLAG IN (LOW : ACTIVE)
Y MODE IC
PULL UP
X MODE IC
CONNECT STFO OUT
OF Y MODE IC TO STFI
OF X MODE IC
XY
; X (HORIZONTAL) / Y (VERTICAL)
SELECT
LOW : X (HORIZONTAL)
ADDRESS GENERATION MODE
HIGH : Y (VERTICAL)
ADDRESS GENERATION MODE
OUTPUT
AD0 - AD10
ADM1, ADM2
MSFO
TSTO
STFO
; 11.2 BIT ADDRESS OUT
; 11.2 BIT ADDRESS OUT
; MULTI-SHIFT FLAG OUT (LOW : ACTIVE)
; TEST
; STREAM FLAG OUT (LOW : ACTIVE)
INPUT / OUTPUT
DIO
; SERIAL DATA
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