MT6589 查看數據表（PDF） - MediaTek Inc
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MT6589 Datasheet PDF : 53 Pages
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MT6589
HSPA+ Smartphone Application Processor
Technical Brief
Confidential A
GSM circuit switch data
GPRS/EDGE Class 12
Supports SAIC (single antenna
interference cancellation) technology
Supports VAMOS (Voice services over
Adaptive Multi-user channels on One
Slot) technology in R9 spec
1.3 Multimedia Features
Display
Supports landscape or portrait panel
Image
resolution up to WXGA (1280x800)
Integrated image signal processor
Supports 8/9/16/18/24-bit host interface
supports 13 MP up to 15fps
(MIPI DBI)
Supports electronic image stabilization
Supports 8/9/16/24/32-bit serial
Supports video stabilization
interfaces
Supports local contrast enhancement
Supports 16/18/24-bit RGB interfaces
Supports preference color adjustment
(MIPI DPI)
Supports noise reduction
MIPI DSI interface (4 data lanes)
Supports multiple frame noise reduction
Embedded LCD gamma correction
for video recording
Supports true colors
Supports lens shading correction
4 overlay layers with per-pixel alpha
Supports auto sensor defect pixel
channel and gamma table
correction
Supports spatial and temporal dithering
Supports AE/AWB/AF
Supports side-by-side format output to
Supports edge enhancement
stereo 3D panel in both portrait and
(sharpness)
landscape modes
Supports face detection and visual
Supports external HDMI/MHL Tx bridge
tracking
with 720p video output
Supports multiple frame blending for
Supports color enhancement
multi-motion special effect
Supports adaptive contrast
Supports zero shutter delay image
enhancement
capture
Supports image/video/graphic
Supports capturing full size image when
sharpness enhancement
recording video (up to 8M sensor)
Supports dynamic backlight scaling
Supports capturing stereo image without
bridge IC
Graphics
Supports stereo video recording without
OpenGL ES 1.1/2.0 3D graphic
bridge IC
accelerator capable of processing 50M
Supports MIPI CSI-2 high-speed
tri/sec and 572M pixel/sec @ 286MHz
camera serial interface with 4 data lane
(effective pixel rate: 1,430M pixel/sec.)
(for main) + 2 data lane (for stereo) + 2
OpenVG1.1 vector graphics accelerator
data lane (for sub)
2D graphics hardware accelerator
Supports Xenon flash
MediaTek Confidential
© 2012 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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