STI5512 查看數據表（PDF） - STMicroelectronics

零件编号

产品描述 (功能)

生产厂家

STI5512

SET TOP BOX BACKEND DECODER WITH INTEGRATED HOST PROCESSOR

STMicroelectronics 

CONFIDENTIAL STi5512

Memory subsystem

The STi5512 on-chip memory system provides 200 Mbytes/s internal data bandwidth, supporting pipelined 2-cycle

internal memory access at 20 ns cycle times at 60 MHz. The STi5512 memory subsystem consists of instruction and

data caches, SRAM and an external memory interface (EMI).

The STi5512 product has 4 Kbytes of on-chip SRAM. The advantage of this is the ability to store on-chip any time-

critical code, such as interrupt routines, software kernels or device drivers, and even frequently used data.

The instruction and data caches are direct mapped with a write-back system for the data cache. The caches support

burst accesses to the external memories for refill and write-back which are effective for increasing performance with

page-mode DRAM memories. The data cache may also be configured as an additional 2 Kbytes of internal SRAM.

The STi5512 EMI controls access to the external memory and peripherals including the DMA data ports. It can access

a 16 Mbyte physical address space in each of the three memory banks, or greater if DRAM is used. It provides

sustained transfer rates of up to 80 Mbytes/s for SRAM, and up to 40 Mbytes/s using page-mode DRAM.

The 32-bit programmable EMI supports ROM, SRAM and DRAM/SDRAM for the ST20. SDRAM is supported at the

CPU clock rate, 60 MHz. The STi5512 supports boot bank width ROM/Flash population options using the address shift

mechanism.

The SDRAM interface supports the use of two 16 Mbits or one 64 Mbits of external 100 MHz SDRAM. This memory is

used to store the display data generated by the MPEG decoder and the CPU and read by the display unit.

Interrupt subsystem

The STi5512 interrupt subsystem supports eight prioritized interrupt levels. Four external interrupt pins are provided.

Level assignment logic allows any of the internal or external interrupts to be assigned to any interrupt level. Interrupt

level sharing is supported for level-sensitive interrupts.

Serial communications

To facilitate the connection of this system to a modem for a pay-per-view type system and other peripherals, two UARTs

(ASC2s) are included in the device. The UARTs provide an asynchronous serial interface and can be programmed to

support a range of baud rates and data formats, for example, data size, stop bits and parity. The UARTs are buffered

with 16 byte FIFOs for transmit and receive data.

Two synchronous serial communications (SSC2) interfaces are provided on the device. These can be used to control,

via an I2C or SPI bus, the tuner, Link-IC, E2PROM (if used) and the remote control devices in the application.

Block move engine

High performance block data transfer can be performed as a memory to memory DMA operation using the block move

module.

IEEE 1284 interface

An 8-bit wide parallel interface (conforming to the IEEE 1284 standard) supports a high speed data input/output port to

and from the set top receiver. The interface has a dedicated DMA controller to transfer data between memory and the

port with little CPU overhead.

The STi5512 has a new mode called ‘1284_master_mode’. In this mode, pairs of the 1284 interface swap functionality

and direction. The control signal for this mode comes from bit 15 of the EMIConfigpadlogic signal. When low, the 1284

is in slave mode and behaves as on the STi5510. When high, the 1284 is in master mode.

7110123 B

9/23

Share Link: