CAT1163 查看數據表（PDF） - Catalyst Semiconductor => Onsemi

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CAT1163

Supervisory Circuit with I2C Serial CMOS EEPROM, Precision Reset Controller and Watchdog Timer

Catalyst Semiconductor => Onsemi 

CAT1163

Acknowledge Polling

Disabling of the inputs can be used to take advantage of

the typical write cycle time. Once the stop condition is

issued to indicate the end of the host’s write opration the

CAT1163 initiates the internal write cycle. ACK polling

can be initiated immediately. This involves issuing the

start condition followed by the slave address for a write

operation. If the CAT1163 is still busy with the write

operation, no ACK will be returned. If a write operation

has completed, an ACK will be returned and the host can

then proceed with the next read or write operation.

WRITE PROTECTION

The Write Protection feature allows the user to protect

against inadvertent memory array programming. If the

WP pin is tied to VCC, the entire memory array is

protected and becomes read only. The CAT1163 will

accept both slave and byte addresses, but the memory

location accessed is protected from programming by the

device’s failure to send an acknowledge after the first

byte of data is received.

Read Operations

The READ operation for the CAT1163 is initiated in the

same manner as the write operation with one exception,

that R/W bit is set to one. Three different READ operations

are possible: Immediate/Current Address READ,

Selective/Random READ and Sequential READ.

Figure 9. Immediate Address Read Timing

SCL

SDA

S

T

S

BUS ACTIVITY: A

SLAVE

T

MASTER R ADDRESS

O

T

P

SDA LINE S

P

A

N

C

DATA

O

K

A

C

K

8

9

8TH BIT

DATA OUT

NO ACK

STOP

9

Doc No. 3003, Rev. C

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