PD69108F 查看數據表（PDF） - Microsemi Corporation

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PD69108F

8 PORTS PSE POE MANAGER

Microsemi Corporation 

TM

SPI Detailed Timing Information

®

SPI1 frame

PD69108/F

8 PORTS PSE POE MANAGER

DATASHEET

D3

D1 D2

CS_N

8 SCK clock cycles

D6

Noise Spike

D14

8 SCK clock cycles

D7

D2

8 SCK clock cycles

D8

D4

D5

D13

SCK

MOSI

D9

D10

D12

D15

D11

MISO

Name

D1

D2

D3

Min Delay

45

340 ns

D4

340 ns

D5

2 spi clock cycles

D6

1 spi clock cycles

D7

1 spi clock cycles

D8

1 SPI clock cycles

D9

340 ns

D10

210 ns

D11

D12

D13 1 SPI clock cycles

D14

D15

D3 + 15.5 SPI clock

cycles

Max Delay

714ns

55

140ns

300ns

60ns

D3+23.75 SPI clock

cycles

Description

SPI clock period

SPI duty cycle

SPI_CS setup to SPI clock Positive Edge (delay after

SPI_CS active signal)

SPI_CS hold to SPI clock Positive Edge (delay before

SPI_CS inactive Signal)

Delay between last SCK in eSPI1 frame and first SCK at

adjacent eSPI1 frame

Between byte 0 (IC addr) and byte 1(addr)

Between byte 1 (addr) and byte 2(data).

Between byte 2 (MS data byte) and byte 3(LS data byte).

MOSI setup time

MOSI hold time

MISO tri-state to valid data from clock positive edge

MISO valid data to tri-state from SPI_CS positive edge

SPI_CS width (Delay eSPI1 frame to adjacent eSPI1 frame)

Filtered Glitch Width

MISO tri-state from SPI_CS Negative Edge to valid data

Copyright © 2013

Microsemi

10

Rev. 1.6

Analog Mixed Signal Group

1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308

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