AD9684 查看數據表（PDF） - Analog Devices

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AD9684

14-Bit, 500 MSPS LVDS, Dual Analog-to-Digital Converter

Analog Devices 

AD9684

Product

Overview

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Documentation

Design

Resources

Discussion

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Data Sheet

VIN±x

APERTURE DELAY

N

N+x

N + 36

N + 37

N + 38

SYNC+

SYNC–

CLK+

CLK–

DCO± (DATA CLOCK OUTPUT)

0° PHASE ADJUST

SYNCHRONOUS LOW TO HIGH TRANSITIONS OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF

THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET

CONSTANT LATENCY = X CLK CYCLES

tDCO

tPD

tCLK

DCO± (DATA CLOCK OUTPUT)

180° PHASE ADJUST

STATUS BIT SELECTED BY

REGISTER 0x559, BITS[2:0]

IN THE REGISTER MAP

STATUS+

(OVERRANGE/STATUS BIT)

STATUS–

STATUS STATUS

D13±

D13

D13

tSKEWR

tSKEWF

CONVERTER 0

SAMPLE

[N]

CONVERTER 1

SAMPLE

[N]

CONVERTER 0

SAMPLE

[N + 1]

CONVERTER 1

SAMPLE

[N + 1]

CONVERTER 0

SAMPLE

[N + 2]

STATUS STATUS STATUS STATUS STATUS STATUS

D13

D13

D13

D13

D13

D13

D0±

D0

D0

D0

D0

D0

D0

D0

D0

Figure 5. Parallel Interleaved Mode—Two Converters, ≤14-Bit Data, Output Sample Rate < 625 MSPS

Rev. 0 | Page 10 of 64

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