ISPLS1024-60LH/883 查看數據表（PDF） - Lattice Semiconductor
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ISPLS1024-60LH/883 Datasheet PDF : 12 Pages
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Specifications ispLSI 1024/883
Pin Description
NAME
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
JLCC
PIN NUMBERS
22, 23, 24, 25,
26, 27, 28, 29,
30, 31, 32, 33,
37, 38, 39, 40,
41, 42, 43, 44,
45, 46, 47, 48,
56, 57, 58, 59,
60, 61, 62, 63,
64, 65, 66, 67,
3, 4, 5, 6,
7, 8, 9, 10,
11, 12, 13, 14
IN 4 - IN 5
2, 15
ispEN
19
SDI/IN 01
21
MODE/IN 31 55
SDO/IN 11
34
SCLK/IN 21
49
NC2
—
DESCRIPTION
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
Input - These pins are dedicated input pins to the device.
Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. The MODE, SDI, SDO
and SCLK options become active.
Input - This pin performs two functions. When ispEN is logic low, it
functions as an input pin to load programming data into the device.
SDI/IN 0 is also used as one of the two control pins for the isp state
machine. It is a dedicated input pin when ispEN is logic high.
Input - This pin performs two functions. When ispEN is logic low, it
functions as pin to control the operation of the isp state machine. It is a
dedicated input pin when ispEN is logic high.
Output/Input - This pin performs two functions. When ispEN is logic low,
it functions as an output pin to read serial shift register data. It is a
dedicated input pin when ispEN is logic high.
Input - This pin performs two functions. When ispEN is logic low, it
functions as a clock pin for the Serial Shift Register. It is a dedicated
input pin when ispEN is logic high.
No Connect
RESET
Y0
Y1
Y2
Y3
GND
20
16
54
51
50
1, 18, 35, 52
Active Low (0) Reset pin which resets all of the GLB and I/O registers in
the device.
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all of the GLBs on the device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.
Ground (GND)
VCC
17, 36, 53, 68
VCC
1. Pins have dual function capability.
2. NC pins are not to be connected to any active signals, Vcc or GND.
Table 2 - 0002C-24 mil
10
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