ISPLS1024-60LH/883 查看數據表（PDF） - Lattice Semiconductor

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ISPLS1024-60LH/883

In-System Programmable High Density PLD

Lattice Semiconductor 

Specifications ispLSI 1024/883

Maximum GRP Delay vs GLB Loads

6

ispLSI 1024-60

5

4

3

2

1

0

4

8

12

GLB Loads

16

0126A-80-24-mil.eps

Power Consumption

Power consumption in the ispLSI 1024/883 device de- used. Figure 3 shows the relationship between power

pends on two primary factors: the speed at which the and operating speed.

device is operating, and the number of Product Terms

Figure 3. Typical Device Power Consumption vs fmax

200

ispLSI 1024

150

100

50

0 10 20 30 40 50 60 70 80

fmax (MHz)

Notes: Configuration of Six 16-bit Counters

Typical Current at 5V, 25˚C

ICC can be estimated for the ispLSI 1024 using the following equation:

ICC = 42 + (# of PTs * 0.45) + (# of nets * Max. freq * 0.008) where:

# of PTs = Number of Product Terms used in design

# of nets = Number of Signals used in device

Max. freq = Highest Clock Frequency to the device

The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 2 GLB loads on

average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the

program in the device, the actual ICC should be verified.

0127A-24-80-isp

9

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