KSZ8081RNACA 查看數據表（PDF） - Micrel

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KSZ8081RNACA

10Base-T/100Base-TX PHY with RMII Support

Micrel 

Micrel, Inc.

KSZ8081RNA/KSZ8081RND

Pin Description (Continued)

Pin Number

Pin Name

Type(1)

16

REF_CLK

Ipd/O

17

RXER

Ipd/O

18

INTRP

Ipu/Opu

19

TXEN

I

20

TXD0

I

21

TXD1

I/O

22

GND

Gnd

LED0 /

23

Ipu/O

ANEN_SPEED

Pin Function

RMII – 25MHz Mode:

This pin provides the 50MHz RMII reference clock

output to the MAC.

RMII – 50MHz Mode: This pin is a no connect.

For unmanaged mode (power-up default setting),

KSZ8081RNA is in RMII – 25MHz mode and outputs the 50MHz RMII

reference clock on this pin.

KSZ8081RND is in RMII – 50MHz mode and does not use this pin.

After power-up, both KSZ8081RNA and KSZ8081RND can be programmed to either

25MHz mode or 50MHz mode using PHY register 1Fh bit [7].

See also XI (pin 8).

RMII Receive Error output

At the de-assertion of reset, this pin needs to latch in a pull-down value for normal

operation. If MAC side pulls this pin high, see Register 16h, Bit [15] for solution.

Interrupt output: Programmable interrupt output

This pin has a weak pull-up, is open drain, and requires an external 1.0kΩ pull-up

resistor.

RMII Transmit Enable input

RMII Transmit Data Input[0](3)

RMII Transmit Data Input[1](3)

NAND Tree mode:

NAND Tree output pin

Ground

LED output:

Programmable LED0 output

Config mode: Latched as auto-negotiation enable (register 0h, bit [12]) and

Speed (register 0h, bit [13]) at the de-assertion of reset.

See the “Strapping Options” section for details.

The LED0 pin is programmable using register 1Fh bits

[5:4], and is defined as follows.LED mode = [00]

Link/Activity

Pin State

LED Definition

No link

High

OFF

Link

Low

ON

Activity

Toggle

Blinking

LED mode = [01]

Link

Pin State

No link

High

Link

Low

LED Definition

OFF

ON

LED mode = [10], [11]

Reserved

24

RST#

Ipu Chip reset (active low)

PADDLE

GND

Gnd Ground

Notes:

2. RMII RX Mode: The RXD[1:0] bits are synchronous with the 50MHz RMII Reference Clock. For each clock period in which CRS_DV is asserted,

two bits of recovered data are sent by the PHY to the MAC.

3. RMII TX Mode: The TXD[1:0] bits are synchronous with the 50MHz RMII Reference Clock. For each clock period in which TXEN is asserted, two

bits of data are received by the PHY from the MAC.

February 6, 2014

10

Revision 1.1

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