Q67007-A9291 查看數據表（PDF） - Infineon Technologies

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Q67007-A9291

5-V Low Drop Fixed Voltage Regulator

Infineon Technologies 

TLE 4278 G

Reset Timing

The power-on reset delay time is defined by the charging time of an external capacitor

CD which can be calculated as follows:

CD = (∆trd × ID,c)/∆V

(1)

Definitions:

• CD = delay capacitor

• ∆trd = delay time

• ID,c = charge current, typical 5 µA

• ∆V = VDU, typical 1.9 V

• VDU = upper delay switching threshold at CD for reset delay time

The reset reaction time trr is the time it takes the voltage regulator to set the reset out

LOW after the output voltage has dropped below the reset threshold. It is typically 1 µs

for delay capacitor of 47 nF. For other values for CD the reaction time can be estimated

using Equation (2):

trr ≈ 20 s/F × CD

(2)

VΙ

VQ

VD

t rd

t rr

VRO

t

< t rr

V Q, rt

dV

dt

=

Ι D,c

CD

t

V DU

V DRL

t

Power-on-Reset

Thermal

Shutdown

Voltage Dip

at Input

Undervoltage Secondary Overload

Spike at Output

Figure 5 Reset Timing (watchdog disabled)

t

AED03010

Data Sheet

11

Rev. 1.3, 2005-04-29

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