AD7988-1BRMZ-RL7 查看數據表（PDF） - Analog Devices

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AD7988-1BRMZ-RL7

16-Bit Lower Power PulSAR ADCs in MSOP/LFCSP (QFN)

Analog Devices 

AD7988-1/AD7988-5

500µA IOL

TO SDO

CL

20pF

1.4V

500µA IOH

Figure 2. Load Circuit for Digital Interface Timing

X% VIO1

tDELAY

VIH2

VIL2

Y% VIO1

tDELAY

VIH2

VIL2

1FOR VIO ≤ 3.0V, X = 90 AND Y = 10; FOR VIO > 3.0V X = 70, AND Y = 30.

2MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS

SPECIFICATIONS IN TABLE 3.

Figure 3. Voltage Levels for Timing

Data Sheet

Rev. B | Page 6 of 24

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