BD82HM55QMNT 查看數據表（PDF） - Intel
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BD82HM55QMNT Datasheet PDF : 934 Pages
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13.2
13.3
13.4
13.5
13.6
13.7
13.8
13.1.34FDLEN—Feature Detection Capability Length
(LPC I/F—D31:F0) ................................................................................ 478
13.1.35FDVER—Feature Detection Version
(LPC I/F—D31:F0) ................................................................................ 478
13.1.36FDVCT—Feature Vector
(LPC I/F—D31:F0) ................................................................................ 479
13.1.37RCBA—Root Complex Base Address Register
(LPC I/F—D31:F0) ................................................................................ 479
DMA I/O Registers........................................................................................... 480
13.2.1 DMABASE_CA—DMA Base and Current Address Registers .......................... 482
13.2.2 DMABASE_CC—DMA Base and Current Count Registers ............................. 482
13.2.3 DMAMEM_LP—DMA Memory Low Page Registers ....................................... 483
13.2.4 DMACMD—DMA Command Register ........................................................ 483
13.2.5 DMASTA—DMA Status Register .............................................................. 484
13.2.6 DMA_WRSMSK—DMA Write Single Mask Register...................................... 484
13.2.7 DMACH_MODE—DMA Channel Mode Register ........................................... 485
13.2.8 DMA Clear Byte Pointer Register............................................................. 486
13.2.9 DMA Master Clear Register .................................................................... 486
13.2.10DMA_CLMSK—DMA Clear Mask Register .................................................. 486
13.2.11DMA_WRMSK—DMA Write All Mask Register ............................................ 487
Timer I/O Registers ......................................................................................... 487
13.3.1 TCW—Timer Control Word Register ......................................................... 488
13.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register........................... 490
13.3.3 Counter Access Ports Register ................................................................ 491
8259 Interrupt Controller (PIC) Registers ........................................................... 491
13.4.1 Interrupt Controller I/O MAP .................................................................. 491
13.4.2 ICW1—Initialization Command Word 1 Register ........................................ 492
13.4.3 ICW2—Initialization Command Word 2 Register ........................................ 493
13.4.4 ICW3—Master Controller Initialization Command
Word 3 Register ................................................................................... 493
13.4.5 ICW3—Slave Controller Initialization Command
Word 3 Register ................................................................................... 494
13.4.6 ICW4—Initialization Command Word 4 Register ........................................ 494
13.4.7 OCW1—Operational Control Word 1 (Interrupt Mask)
Register .............................................................................................. 495
13.4.8 OCW2—Operational Control Word 2 Register ............................................ 495
13.4.9 OCW3—Operational Control Word 3 Register ............................................ 496
13.4.10ELCR1—Master Controller Edge/Level Triggered Register ........................... 497
13.4.11ELCR2—Slave Controller Edge/Level Triggered Register ............................. 498
Advanced Programmable Interrupt Controller (APIC)............................................ 499
13.5.1 APIC Register Map................................................................................ 499
13.5.2 IND—Index Register ............................................................................. 499
13.5.3 DAT—Data Register .............................................................................. 500
13.5.4 EOIR—EOI Register .............................................................................. 500
13.5.5 ID—Identification Register ..................................................................... 501
13.5.6 VER—Version Register .......................................................................... 501
13.5.7 REDIR_TBL—Redirection Table ............................................................... 502
Real Time Clock Registers................................................................................. 504
13.6.1 I/O Register Address Map ...................................................................... 504
13.6.2 Indexed Registers ................................................................................ 505
13.6.2.1 RTC_REGA—Register A ............................................................ 506
13.6.2.2 RTC_REGB—Register B (General Configuration) .......................... 507
13.6.2.3 RTC_REGC—Register C (Flag Register) ...................................... 508
13.6.2.4 RTC_REGD—Register D (Flag Register) ...................................... 508
Processor Interface Registers ............................................................................ 509
13.7.1 NMI_SC—NMI Status and Control Register ............................................... 509
13.7.2 NMI_EN—NMI Enable (and Real Time Clock Index)
Register .............................................................................................. 510
13.7.3 PORT92—Fast A20 and Init Register ....................................................... 510
13.7.4 COPROC_ERR—Coprocessor Error Register .............................................. 510
13.7.5 RST_CNT—Reset Control Register........................................................... 511
Power Management Registers (PM—D31:F0) ....................................................... 512
13.8.1 Power Management PCI Configuration Registers
(PM—D31:F0) ...................................................................................... 512
13.8.1.1 GEN_PMCON_1—General PM Configuration 1 Register
(PM—D31:F0) ........................................................................ 513
Datasheet
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