BD82HM55QMNT 查看數據表（PDF） - Intel
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BD82HM55QMNT Datasheet PDF : 934 Pages
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16.2
16.1.17PWR_CAPID—PCI Power Management Capability ID
Register (USB EHCI—D29:F0, D26:F0) .................................................... 654
16.1.18NXT_PTR1—Next Item Pointer #1 Register
(USB EHCI—D29:F0, D26:F0)................................................................. 654
16.1.19PWR_CAP—Power Management Capabilities Register
(USB EHCI—D29:F0, D26:F0)................................................................. 655
16.1.20PWR_CNTL_STS—Power Management Control/
Status Register (USB EHCI—D29:F0, D26:F0) .......................................... 656
16.1.21DEBUG_CAPID—Debug Port Capability ID Register
(USB EHCI—D29:F0, D26:F0)................................................................. 657
16.1.22NXT_PTR2—Next Item Pointer #2 Register
(USB EHCI—D29:F0, D26:F0)................................................................. 657
16.1.23DEBUG_BASE—Debug Port Base Offset Register
(USB EHCI—D29:F0, D26:F0)................................................................. 657
16.1.24USB_RELNUM—USB Release Number Register
(USB EHCI—D29:F0, D26:F0)................................................................. 657
16.1.25FL_ADJ—Frame Length Adjustment Register
(USB EHCI—D29:F0, D26:F0)................................................................. 658
16.1.26PWAKE_CAP—Port Wake Capability Register
(USB EHCI—D29:F0, D26:F0)................................................................. 659
16.1.27LEG_EXT_CAP—USB EHCI Legacy Support Extended
Capability Register (USB EHCI—D29:F0, D26:F0)...................................... 660
16.1.28LEG_EXT_CS—USB EHCI Legacy Support Extended
Control / Status Register (USB EHCI—D29:F0, D26:F0) ............................. 661
16.1.29SPECIAL_SMI—Intel Specific USB 2.0 SMI Register
(USB EHCI—D29:F0, D26:F0)................................................................. 663
16.1.30ACCESS_CNTL—Access Control Register
(USB EHCI—D29:F0, D26:F0)................................................................. 664
16.1.31EHCIIR1—EHCI Initialization Register 1
(USB EHCI—D29:F0, D26:F0)................................................................. 665
16.1.32FLR_CID—Function Level Reset Capability ID
(USB EHCI—D29:F0, D26:F0)................................................................. 665
16.1.33FLR_NEXT—Function Level Reset Next Capability Pointer
(USB EHCI—D29:F0, D26:F0)................................................................. 665
16.1.34FLR_CLV—Function Level Reset Capability Length and
Version (USB EHCI—D29:F0, D26:F0) ..................................................... 666
16.1.35FLR_CTRL—Function Level Reset Control Register
(USB EHCI—D29:F0, D26:F0)................................................................. 667
16.1.36FLR_STS—Function Level Reset Status Register
(USB EHCI—D29:F0, D26:F0)................................................................. 667
Memory-Mapped I/O Registers .......................................................................... 668
16.2.1 Host Controller Capability Registers......................................................... 668
16.2.1.1 CAPLENGTH—Capability Registers Length Register ....................... 669
16.2.1.2 HCIVERSION—Host Controller Interface Version Number
Register ................................................................................. 669
16.2.1.3 HCSPARAMS—Host Controller Structural Parameters .................... 669
16.2.1.4 HCCPARAMS—Host Controller Capability Parameters
Register ................................................................................. 670
16.2.2 Host Controller Operational Registers ...................................................... 671
16.2.2.1 USB2.0_CMD—USB 2.0 Command Register................................. 672
16.2.2.2 USB2.0_STS—USB 2.0 Status Register....................................... 675
16.2.2.3 USB2.0_INTR—USB 2.0 Interrupt Enable Register........................ 677
16.2.2.4 FRINDEX—Frame Index Register ............................................... 678
16.2.2.5 CTRLDSSEGMENT—Control Data Structure Segment
Register ................................................................................. 678
16.2.2.6 PERIODICLISTBASE—Periodic Frame List Base Address
Register ................................................................................. 679
16.2.2.7 ASYNCLISTADDR—Current Asynchronous List Address
Register ................................................................................. 679
16.2.2.8 CONFIGFLAG—Configure Flag Register ....................................... 680
16.2.2.9 PORTSC—Port N Status and Control Register............................... 680
16.2.3 USB 2.0-Based Debug Port Registers ....................................................... 684
16.2.3.1 CNTL_STS—Control/Status Register........................................... 685
16.2.3.2 USBPID—USB PIDs Register ..................................................... 687
16.2.3.3 DATABUF[7:0]—Data Buffer Bytes[7:0] Register ......................... 687
16.2.3.4 CONFIG—Configuration Register................................................ 687
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