TMP88CM38AFG 查看數據表（PDF） - Toshiba

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TMP88CM38AFG

CMOS 8-Bit Microcontroller

Toshiba 

TMP88CS38/CM38A/CP38A

1.4.1

Clock Generator

The clock generator generates the basic clock which provides the system clocks supplied

to the CPU core and peripheral hardware. It contains oscillation circuit: one for the

high-frequency clock.

The high-frequency (fc) clock can be easily obtained by connecting a resonator between

the XIN/XOUT pin, respectively. Clock input from an external oscillator is also possible. In

this case, external clock is applied to the XIN/XTIN pin not connected. The

TMP88CS38/CM38A/CP38A is not provided an LC oscillation.

High-frequency clock

XIN

XOUT

XIN

XOUT

(Open)

(a) Crystal/Ceramic

resonator

(b) External oscillator

Figure 1.4.2 Examples of Resonator Connection

Note:

Accurate adjustment of the oscillation frequency:

Although hardware to externally and directly monitor the basic clock pulse is not

provided, the oscillation frequency can be adjusted by making the program to output

fixed frequency pulses to the port while disabling all interrupts and monitoring this pulse.

With a system requiring adjustment of the oscillation frequency, the adjusting program

must be created beforehand.

1.4.2

Timing Generator

The timing generator generates from the basic clock the various system clocks supplied

to the CPU core and peripheral hardware. The timing generator provides the following

functions:

1. Generation of main system clock

2. Generation of source clocks for time base timer

3. Generation of source clocks for watchdog timer

4. Generation of internal source clocks for timer/counters TC1 to TC4

5. Generation of warm-up clocks for releasing STOP mode

6. Generation of a clock for releasing reset output

(1) Configuration of timing generator

The timing generator consists of a 21-stage divider with a divided by 3 prescaler, a

main system clock generator, and machine cycle counters.

During reset and at releasing STOP mode, the prescaler and the divider are cleared

to “0”, however, the prescaler is not cleared.

An input clock to the 7th stage of the divider depends on the operating mode.

A divided by 256 of high-frequency clock (fc/28) is input to the 7th stage of the divider.

88CS38-9

2007-09-12

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