C5002 查看數據表（PDF） - Cypress Semiconductor
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C5002 Datasheet PDF : 16 Pages
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C5002
Low Skew Multiple Frequency PCI Clock Generator with EMI Reducing SSCG
Approved Product
Serial Control Registers (Cont.)
Byte 1: Clock Register (1 = enable, 0 = Stopped)
Bit
@Pup
Pin# Description
7
1
-
0= Test Mode ( XIN replaces VCO output ), 1=Normal
6
0
10
Bit 6 Bit 5 PCI9 Frequency
-----------------------------------------
5
HW
10
00
33 MHz
01
66 Mhz
10
16.5 Mhz
11
8.25 MHz
4
0
27
REF-CLK0 mode ( 1 = REF, 0 = PCI0 )
3
HW
27
CLK0 (33.3 MHz = 0, 66.6 MHz = 1)(if Byte 3 Bit 4=0)
2
0
-
SSCG (OFF = 0, ON = 1)
1
1
10
CLK9 ( Active = 1, Forced low = 0 )
0
1
11
CLK8 ( Active = 1, Forced low = 0 )
Byte 2: Clock Register (1 = 66.6 MHz, 0 = 33.3 MHz)
Bit
@Pup Pin# Description
7
HW
11 CLK8 (33.3 MHz = 0, 66.6 MHz = 1)
6
HW
14 CLK7 (33.3 MHz = 0, 66.6 MHz = 1)
5
HW
15 CLK6 (33.3 MHz = 0, 66.6 MHz = 1)
4
HW
18 CLK5 (33.3 MHz = 0, 66.6 MHz = 1)
3
HW
19 CLK4 (33.3 MHz = 0, 66.6 MHz = 1)
2
HW
22 CLK3 (33.3 MHz = 0, 66.6 MHz = 1)
1
HW
23 CLK2 (33.3 MHz = 0, 66.6 MHz = 1)
0
HW
26 CLK1 (33.3 MHz = 0, 66.6 MHz = 1)
Note: HW = Power up programmed via hardware (voltage at pin).
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07014 Rev. **
5/04/2001
Page 8 of 16
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