ADRF6655 查看數據表（PDF） - Analog Devices

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ADRF6655

Broadband Up/Downconverting Mixer with Integrated Fractional-N PLL and VCO

Analog Devices 

ADRF6655

Parameter

SYNTHESIZER SPECIFICATIONS

Fundamental VCO Sensitivity

Spurs

Reference/PFD Spurs

Phase Noise

LO Frequency = 1330 MHz

Integrated Phase Noise

LO Frequency = 1840 MHz

Integrated Phase Noise

PFD Frequency

REFERENCE CHARACTERISTICS

REFIN Input Frequency

REFIN Input Capacitance

REFIN Input Current

REFIN Input Sensitivity

MUXOUT Output Levels

CHARGE PUMP

Pump Current

Output Compliance Range

LOGIC INPUTS

VINH, Input High Voltage

VINL, Input Low Voltage

IINH/IINL, Input Current

CIN, Input Capacitance

POWER SUPPLIES

Voltage Range

Supply Current

Test Conditions/Comments

Synthesizer specifications referenced to 1 × LO4

VCO tuning sensitivity before divide-by-2 or divide-by-3

Measured at LO output

fPFD/2

fPFD

2 × fPFD

4 × fPFD

PFD frequency = 20 MHz4

Min Typ Max Unit

75

MHz/V

−95

dBc

−83

dBc

−85

dBc

−88

dBc

@ 10 kHz offset

@ 100 kHz offset

@ 1 MHz offset

@ 10 MHz offset

10 kHz to 40 MHz integration bandwidth

−85

−114

−138

−154

0.3

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

°rms

@ 10 kHz offset

−83

dBc/Hz

@ 100 kHz offset

−111

dBc/Hz

@ 1 MHz offset

−136

dBc/Hz

@ 10 MHz offset

−152

dBc/Hz

10 kHz to 40 MHz integration bandwidth

0.4

°rms

19.33 20 40 MHz

REFIN, MUXOUT

10 20 160 MHz

4

pF

±100

μA

AC-coupled

0.25 1

3.3 V p-p

VOL (lock detect output selected)

0.25 V

VOH (lock detect output selected)

2.7

V

CP

Charge pump current adjustable using Register 4 and/or

RSET (see Pin 5 description)

500

μA

1

2.8 V

CLK, DATA, LE

1.4

3.3 V

0

0.7 V

±1

μA

3

pF

VCC1, VCC2, VCCLO

4.75 5

5.25 V

LO output buffer disabled

PLL only

115

mA

Normal TX mode, IP3SET = 3.2 V, fLO ≤1530 MHz (divide-by-3)

310

mA

Normal TX mode, IP3SET = 3.2 V, fLO > 1530 MHz (divide-by-2)

270

mA

Normal RX mode, IP3SET = open, fLO ≤ 1530 MHz (divide-by-3)

285

mA

Normal RX mode, IP3SET = open, fLO > 1530 MHz (divide-by-2)

245

mA

Power-down mode

15

mA

1 Internal LO path divider programmed via serial interface. See the LO Signal Chain section for additional information.

2 See the External LO Interface section.

3 Improved return loss can be achieved using external matching. See the Circuit Description section for more details.

4 Measured on standard evaluation board with 1.5 kHz loop filter (C13 = 47 nF, C14 = 0.1 μF, C15 = 4.7 μF, R9 = 270 Ω, R10 = 68 Ω).

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