LTC2262IUJ-12-PBF 查看數據表（PDF） - Linear Technology

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LTC2262IUJ-12-PBF

12-Bit, 150Msps Ultralow Power 1.8V ADC

Linear Technology 

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2262-12: IOVDD vs Sample

Rate, 5MHz Sine Wave Input,

–1dB, 5pF on Each Data Output

45

40

3.5mA LVDS

35

30

25

1.75mA LVDS

20

15

10

1.8V CMOS

5

0

1.2V CMOS

0 25 50 75 100 125 150

SAMPLE RATE (Msps)

226212 G14

LTC2262-12: SNR vs SENSE,

fIN = 5MHz, –1dB

71

70

69

68

67

66

0.6 0.7 0.8 0.9 1 1.1 1.2 1.3

SENSE PIN (V)

226212 G15

LTC2262-12

LTC2262-12: SNR vs Sample Rate

and Digital Output Mode,

30MHz Sine Wave Input, –1dB

71

LVDS

CMOS

70

DDR CMOS

69

68

67

0 25 50 75 100 125 150

SAMPLE RATE (Msps)

226212 G18

PIN FUNCTIONS

PINS THAT ARE THE SAME FOR ALL DIGITAL OUTPUT

MODES

AIN+ (Pin 1): Positive Differential Analog Input.

AIN– (Pin 2): Negative Differential Analog Input.

GND (Pin 3): ADC Power Ground.

REFH (Pins 4, 5): ADC High Reference. Bypass to Pins

6, 7 with a 2.2μF ceramic capacitor and to ground with a

0.1μF ceramic capacitor.

REFL (Pins 6, 7): ADC Low Reference. Bypass to Pins

4, 5 with a 2.2μF ceramic capacitor and to ground with a

0.1μF ceramic capacitor.

PAR/SER (Pin 8): Programming Mode Selection Pin. Con-

nect to ground to enable the serial programming mode.

CS, SCK, SDI, SDO become a serial interface that control

the A/D operating modes. Connect to VDD to enable the

parallel programming mode where CS, SCK, SDI become

parallel logic inputs that control a reduced set of the A/D

operating modes. PAR/SER should be connected directly

to ground or the VDD of the part and not be driven by a

logic signal.

VDD (Pins 9, 10, 40): 1.8V Analog Power Supply. Bypass

to ground with 0.1μF ceramic capacitors. Pins 9 and 10

can share a bypass capacitor.

ENC+ (Pin 11): Encode Input. Conversion starts on the

rising edge.

ENC– (Pin 12): Encode Complement Input. Conversion

starts on the falling edge.

CS (Pin 13): In serial programming mode, (PAR/SER =

0V), CS is the serial interface chip select input. When

CS is low, SCK is enabled for shifting data on SDI into

the mode control registers. In the parallel programming

mstaobdieliz(ePrA. RW/hSeEnRC=SVisDlDo)w, C, tShecocnlotcrokldsuthtyeccylcolceksdtaubtyiliczeyrclies

turned off. When CS is high, the clock duty cycle stabilizer

is turned on. CS can be driven with 1.8V to 3.3V logic.

SCK (Pin 14): In serial programming mode, (PAR/SER =

0V), SCK is the serial interface clock input. In the parallel

programming mode (PAR/SER = VDD), SCK controls the

digital output mode. When SCK is low, the full-rate CMOS

output mode is enabled. When SCK is high, the double

data rate LVDS output mode (with 3.5mA output current)

is enabled. SCK can be driven with 1.8V to 3.3V logic.

SDI (Pin 15): In serial programming mode, (PAR/SER =

0V), SDI is the serial interface data input. Data on SDI is

clocked into the mode control registers on the rising edge

of SCK. In the parallel programming mode (PAR/SER =

VDD), SDI can be used to power down the part. When SDI

is low, the part operates normally. When SDI is high, the

226212p

11

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