MTV112A 查看數據表（PDF） - Myson Century Inc

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MTV112A

8051 Embedded CRT Monitor Controller MASK Version

Myson Century Inc 

MYSON

TECHNOLOGY

MTV112A

(Rev 1.9)

P5OUT

PCTR6

INTFLG

INTEN

INTFLG

INTEN

45h (r/w) P57 P56

46h (w) X

X

50h (r/w) HPRchg VPRchg

60h (w) EHPR EVPR

51h(r/w) X

X

61h(w) X

X

P55

X

HPLchg

EHPL

X

X

P54

X

VPLchg

EVPL

X

X

P53

X

HFchg

EHF

X

X

P52

X

VFchg

EVF

X

X

P51

CLPsel

FIFOI

EFIFO

X

X

P50

HALFHsel

MI

EMI

VSYNC

EVSI

VSYNC

HSYNC

Digital Filter

Present

Vpre

Check

Frequency Vfreq

Count

Vself

CVSYNC

Polarity

Vpol

Check

VBpl

High

Frequency

Mask

Polarity Check &

Sync Seperator

Present

Check

CVpre

Hself

Hpol

HBpl

Digital Filter

Hpre

Present Check &

Frequency Count Hfreq

VBLANK

HBLANK

H/V SYNC Processor Block Diagram

PSTUS (r) : The status of polarity, presence and static level for HSYNC and VSYNC.

CVpre = 1 → The extracted CVSYNC is present.

= 0 → The extracted CVSYNC is not present.

Hpol = 1 → HSYNC input is positive polarity.

= 0 → HSYNC input is negative polarity.

Vpol = 1 → VSYNC (CVSYNC) is positive polarity.

= 0 → VSYNC (CVSYNC) is negative polarity.

Hpre = 1 → HSYNC input is present.

= 0 → HSYNC input is not present.

Vpre = 1 → VSYNC input is present.

= 0 → VSYNC input is not present.

Hoff* = 1 → HSYNC input's off-level is high.

= 0 → HSYNC input's off-level is low.

Voff* = 1 → VSYNC input's off-level is high.

= 0 → VSYNC input's off-level is low.

*Hoff and Voff are valid when Hpre=0 or Vpre=0.

HCNTH (r) : H-Freq counter's high bits.

Hovf = 1 → H-Freq counter overflows; this bit is cleared by H/W when condition removed.

HF10 - HF8 : 3 high bits of H-Freq counter.

HCNTL (r) : H-Freq counter's low bits.

10/20

MTV112A Revision 1.9 05/18/2001

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