XC6118 查看數據表（PDF） - TOREX SEMICONDUCTOR

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XC6118

Voltage Detector with Separated Sense Pin & Delay Capacitor Pin

TOREX SEMICONDUCTOR 

XC6118

Series

■OPERATIONAL EXPLANATION

A typical circuit example is shown in Figure 1, and the timing chart of Figure 1 is shown in Figure 2.

*The XC6118N series (N-ch open

drain output) requires a pull-up

resistor for pulling up output.

Figure 1: Typical application circuit example

Sense Pin Voltage: VSEN(MIN.:0V MAX.:6.0V)

Release Voltage: VDF+VHYS

Detect Voltage: VDF

Delay Capacitance Pin Voltage: VCD(MIN.:VSS, MAX.:VIN)

Delay Capacitance Pin Threshold Voltage: VTCD

Output Voltage Pin Voltage: VOUT (MIN.:VSS MAX:VIN)

Figure 2: The timing chart of Figure 1

① As an early state, the sense pin is applied sufficiently high voltage (6.0V MAX.) and the delay capacitance (Cd) is charged

to the power supply input voltage, (VIN: 1.0V MIN., 6.0V MAX.). While the sense pin voltage (VSEN) starts dropping to

reach the detect voltage (VDF) (VSEN>VDF), the output voltage (VOUT) keeps the “High” level (=VIN).

* If a pull-up resistor of the XC6118N series (N-ch open drain) is connected to added power supply different from the input

voltage pin, the “High” level will be a voltage value where the pull-up resistor is connected.

② When the sense pin voltage keeps dropping and becomes equal to the detect voltage (VSEN =VDF), an N-ch transistor (M1)

for the delay capacitance (Cd) discharge is turned ON, and starts to discharge the delay capacitance (Cd). An inverter

(Inv.1) operates as a comparator of the reference voltage VIN, and the output voltage changes into the “Low” level (=VSS).

The detect delay time [tDF] is defined as time which ranges from VSEN=VDF to the VOUT of “Low” level (especially, when the

Cd pin is not connected: tDF0).

③ While the sense pin voltage keeps below the detect voltage, the delay capacitance (Cd) is discharged to the ground voltage

(=VSS) level. Then, the output voltage maintains the “Low” level while the sense pin voltage increases again to reach the

release voltage (VSEN< VDF +VHYS).

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