LV5256GP 查看數據表（PDF） - SANYO -> Panasonic
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LV5256GP Datasheet PDF : 9 Pages
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Pin Functions
Pin No.
Pin Name
1
NC
2
6
3
ONOFF
LV5256GP
Description
No connection. Must be kept open.
ON/OFF signal input pin.
Threshold level is TTL level.
Maximum withstand voltage is VDD.
Equivalent Circuit
VDD
3
4
VIN
5
DU_SLE
7
PGND
8
SW
9
VOUT
10
VOUT-5
11
OCP
12
REG_O
Power supply pin of the IC. Apply the input voltage.
Step-up/down switching pin. The IC goes in step-up mode
by connecting this pin to REG_O pin, and in step-down
mode by connecting this pin to GND or leaving this pin
open. An internal pull-down resistor (200kΩ) is provided
between DU_SEL and GND pins.
Power ground pin. The source of the output transistor
(Nch-MOSFET) is connected.
Switching element. A 0.7Ω (typ) Nch switch is inserted
between this pin and PGND, and a 0.7Ω (typ) Pch switch is
connected between this pin and VOUT. In step-down
mode, insert an inductor between the switching node and
power supply output, and in step-up mode insert an
inductor between this pin and power supply input.
Source potential of the internal Pch-MOSFET. In
step-down mode, apply the input voltage. In step-up mode,
apply the power supply voltage.
Internal Pch-MOSFET gate suplly voltage generation pin.
Used to generate a voltage with a level equal to VOUT pin
voltage-5V by the internal LDO with OCP.
Overcurrent detection timer setup pin. Connect a capacitor
between this pin and ground to define the time interval
between the beginning of the overcurrent state and the IC
latches off. The capacitor is charged by the 10µA internal
constant current source. If the OCP_SEL pin is kept open
or connected to GND, the IC identifies a short-circuit and
starts the timer counter when the voltage at the IN pin falls
below 0.8 times the voltage of Vref, TRAC_IN or SS,
whichever is lower. If the OCP_SEL pin is connected to
REG_O, the IC compares the voltage at the IN pin with 0.4
times the voltage. When the voltage at this pin goes
beyond 1.25V, the IC latches off. The latch-off state is
reset by the off signal at the ON/OFF pin or the UVLO lock.
3.3V regulator output pin.
VDD
5
200kΩ
VOUT
8
VIN
REG_O
10µA
10kΩ
11
500Ω
1kΩ
VIN
50Ω
12
32kΩ
20kΩ
Continued on next page.
No.A1277-6/9
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