ADCMP600/ADCMP601/ADCMP602
OUTLINE DIMENSIONS
2.20
2.00
1.80
1.35
5
4
2.40
1.25
2.10
1.15
1
2
3
1.80
0.65 BSC
1.00
0.90
0.70
1.10
0.40
0.80
0.10
0.10 MAX
0.30
SEATING
0.22
PLANE
0.08
0.46
0.36
COPLANARITY
0.15
0.26
0.10
COMPLIANT TO JEDEC STANDARDS MO-203-AA
Figure 27. 5-Lead Thin Shrink Small Outline Transistor Package (SC70)
(KS-5)
Dimensions shown in millimeters
3.00
2.90
2.80
1.70
1.60
1.50
5
4
1
2
3
3.00
2.80
2.60
1.30
1.15
0.90
0.15 MAX
0.05 MIN
1.90
BSC
0.95 BSC
1.45 MAX
0.95 MIN
0.20 MAX
0.08 MIN
0.50 MAX
0.35 MIN
SEATING
PLANE
0.55
10°
5°
0.60
0°
BSC
0.45
0.35
COMPLIANT TO JEDEC STANDARDS MO-178-AA
Figure 28. 5-Lead Small Outline Transistor Package (SOT-23)
(RJ-5)
Dimensions shown in millimeters
Rev. A | Page 14 of 16