PM25LD010 查看數據表（PDF） - Unspecified

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PM25LD010

512Kbit/1 Mbit / 2 Mbit Single Operating Voltage Serial Flash Memory With 100 MHz Dual-Output SPI Bus

Unspecified 

Pm25LD512/010/ 020

REGISTERS (CONTINUED)

PROTECTION MODE

The Pm25LD512/010/020 have two types of write-

protection mechanisms: hardware and software.

These are used to prevent irrelevant operation in a

possibly noisy environment and protect the data

integrity.

HARDWARE WRITE-PROTECTION

The devices provide two hardware write-protection

features:

Table 9. Hardware Write Protection on Status

Register

SRWD

0

1

0

1

WP#

Low

Low

High

High

Status Register

Writable

Protected

Writable

Writable

a. When inputting a program, erase or write status

register instruction, the number of clock pulse is

checked to determine whether it is a multiple of eight

before the executing. Any incomplete instruction

command sequence will be ignored.

b. The Write Protection (WP#) pin provides a

hardware write protection method for BP2, BP1, BP0

and SRWD in the Status Register. Refer to the

STATUS REGISTER description.

c. Write inhibit is 1.8V, all write sequence will be

ignored when Vcc drop to 1.8V and lower

SOFTWARE WRITE PROTECTION

The Pm25LD512/010/020 also provides two software

write protection features:

a. Before the execution of any program, erase or write

status register instruction, the Write Enable Latch

(WEL) bit must be enabled by executing a Write

Enable (WREN) instruction. If the WEL bit is not

enabled first, the program, erase or write register

instruction will be ignored.

b. The Block Protection (BP2, BP1, BP0) bits allow part

or the whole memory area to be write-protected.

Confidential information

Chingis Technology Corp.

9

DRAFT Date: August, 2010, Rev:0.4

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