UPD720114 查看數據表（PDF） - NEC => Renesas Technology
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UPD720114 Datasheet PDF : 32 Pages
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μPD720114
1. PIN INFORMATION
Pin Name
I/O
Buffer Type
Active
Level
Function
X1
I
2.5 V input
30 MHz Crystal oscillator in
X2
O
2.5 V output
30 MHz Crystal oscillator out
SYSRSTB
DP(4:1)
DM(4:1)
DPU
DMU
I
3.3 V Schmitt input
I/O
USB D+ signal I/O
I/O
USB D− signal I/O
I/O
USB D+ signal I/O
I/O
USB D− signal I/O
Low
Asynchronous chip hardware reset
USB’s downstream facing port D+ signal
USB’s downstream facing port D− signal
USB’s upstream facing port D+ signal
USB’s upstream facing port D− signal
BUS_B
I
3.3 V Schmitt input
Power mode select
RREF
A (O) Analog
Reference resistor connection
CSB1
I
5 V tolerant Schmitt input
Low
Port’s over-current status input.
CSB(4:2)
I
3.3 V Schmitt input
Low
Port’s over-current status input
PPB(4:1)
I/O 3.3 V output / input
Low
Port’s power supply control output or hub
configuration input
VBUSM
I
5 V tolerant Schmitt input
Upstream VBUS monitor
AMBER
I/O
3.3V output / input
Amber colored LED control output or port
indicator select
GREEN
O
3.3V output
Green colored LED control output or port
indicator select
LED(4:1)
I/O 3.3V output / input
Low
LED indicator output show downstream port
status or Removable/Non-removable select
TEST
I
3.3 V Schmitt input
Test signal
VDD25OUT
On chip 2.5 V regulator output, it must have a
4.7 μF (or greater) capacitor to VSSREG
VDD33
3.3 V VDD
VDD33REG
3.3 V VDD for on chip 2.5 V regulator input, it must
have a 4.7μF ( or greater) capacitor to VSSREG
VDD25
2.5 V VDD
AVDD
2.5 V VDD for analog circuit
VSS
VSS
VSSREG
On chip 2.5 V regulator VSS
AVSS
VSS for analog circuit
AVSS(R)
VSS for reference resistor, Connect to AVSS.
Remark “5 V tolerant“ means that the buffer is 3 V buffer with 5 V tolerant circuit.
6
Data Sheet S17462EJ4V0DS
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