UPD720130GC-9EU 查看數據表（PDF） - NEC => Renesas Technology

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UPD720130GC-9EU

USB2.0 to IDE Bridge

NEC => Renesas Technology 

µPD720130

1. PIN INFORMATION

Pin Name

I/O

Buffer Type

Active

Level

Function

(1/2)

XIN

I

2.5 V Input

System clock input or oscillator In

XOUT

O

2.5 V Output

Oscillator out

RESETB

I

3.3 V Schmitt Input

Low

Asynchronous reset signaling

MD(1:0)

I

3.3 V Input

Function mode setting

IDECS(1:0)B

O (I/O) 5 V tolerant Output

Low

IDE host chip select

IDEA(2:0)

O (I/O) 5 V tolerant Output

IDE address bus

IDEINT

I (I/O) 5 V tolerant Input

High

IDE interrupt request from device to host

IDEDAKB

O (I/O) 5 V tolerant Output

Low

IDE DMA acknowledge

IDEIORDY

I (I/O) 5 V tolerant Input

High

IDE IO channel ready

IDEIORB

O (I/O) 5 V tolerant Output

Low

IDE IO read strobe

IDEIOWB

O (I/O) 5 V tolerant Output

Low

IDE IO write strobe

IDEDRQ

I (I/O) 5 V tolerant Input

High

IDE DMA request from device to host

IDED(15:0)

I/O 5 V tolerant I/O

IDE data bus

IDERSTB

O (I/O) 5 V tolerant Output

Low

IDE reset from host to device

DCC

I (I/O) 3.3 V Input

IDE controller operational mode setting

DV(1:0)

I (I/O) 3.3 V Input

Device select

CLC

I (I/O) 3.3 V Input

System clock setting

PWR

I (I/O) 3.3 V Input

Bus powered /self-powered select

CMB_BSY

O (I/O) 3.3 V Output

Combo IDE bus busy

CMB_STATE

I (I/O) 3.3 V Input

Combo IDE bus state

DPC

O (I/O) 3.3 V Output

Power control signaling for IDE device

SDA

I/O 3.3 V I/O

Serial ROM data signaling

SCL

VBUS

I/O 3.3 V I/O

I

5 V Schmitt Input Note

Serial ROM clock signaling

VBUS monitoring

DP

I/O USB high speed D+ I/O

DM

I/O USB high speed D− I/O

USB’s high speed D+ signal

USB’s high speed D− signal

RSDP

RSDM

RPU

O

USB full speed D+ Output

O

USB full speed D− Output

A

USB Pull-up control

USB’s full speed D+ signal

USB’s full speed D− signal

USB’s 1.5 kΩ pull-up resistor control

RREF

A

Analog

Reference resistor

SPD

I (I/O) 3.3 V Input

NEC private

SMC

I

3.3 V Input

Scan mode control

TEST(3:0)

I

3.3 V Input

Test mode setting

Note

VBUS pin may be used to monitor for VBUS line even if VDD33, VDD25, and AVDD25 are shut off. System must

ensure that the input voltage level for VBUS pin is less than 3.0 V due to the absolute maximum rating is

not exceeded.

Data Sheet S16302EJ3V0DS

5

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