UPD720130GC-9EU 查看數據表（PDF） - NEC => Renesas Technology
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UPD720130GC-9EU Datasheet PDF : 44 Pages
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µPD720130
2.3 Control Bit in Serial ROM or External Pin Setting
The following tables show IDE status and control bit in serial ROM or external pin setting.
Table 2-3. DV1/DV0, CLC, PWR Setting
No. Device Power Internal
Clock
ATA/ATAPI
Setting in Serial ROM or External Pin
PWR
CLC
DV1
DV0
0
Bus Powered 7.5 MHz No device connected
1
1
1
1
1
ATA
1
1
1
0
2
ATAPI
1
1
0
1
3
Reserved
1
1
0
0
4
60 MHz No device connected
1
0
1
1
5
ATA
1
0
1
0
6
ATAPI
1
0
0
1
7
Reserved
1
0
0
0
8
Self Powered 60 MHz No device connected
0
1
1
1
9
Combo (ATA)
0
1
1
0
10
Combo (ATAPI)
0
1
0
1
11
Reserved
0
1
0
0
12
No device connected
0
0
1
1
13
ATA
0
0
1
0
14
ATAPI
0
0
0
1
15
Auto device detect
0
0
0
0
Remark Setting No. 0, 3, 4, 7, 8, 11, and 12 are prohibited to use.
Data Sheet S16302EJ3V0DS
9
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