UPD720112GK-9EU 查看數據表（PDF） - NEC => Renesas Technology
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UPD720112GK-9EU Datasheet PDF : 32 Pages
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µPD720112
1. PIN INFORMATION
Pin Name
X1_CLK
X2
SYSRSTB
RPU
DP(4:1)
DM(4:1)
DPU
DMU
BUS_SELF
LPWRM
RREF
CSB(4:1)
PPB(4:1)
VBUSM
SCL
SDA/GANG_B
EXROM_EN
AMBER
GREEN
LED(4:1)
TEST
SCAN_MODE
VDD33
VDD25
AVDD
VSS
AVSS
AVSS(R)
I/O
Buffer Type
I
O
I
A (O)
I/O
I/O
I/O
I/O
I
I
A (O)
I
O
I
O
I/O
2.5 V input
2.5 V output
5 V tolerant Schmitt input
USB pull-up control
USB D+ signal I/O
USB D− signal I/O
USB D+ signal I/O
USB D− signal I/O
3.3 V Schmitt input
3.3 V Schmitt input
Analog
5 V tolerant input
5 V tolerant N-ch open drain
5 V tolerant Schmitt input
3.3 V output
3.3 V Schmitt I/O
I
3.3 V Schmitt input
O
5 V tolerant output
O
5 V tolerant output
O
5 V tolerant output
I
3.3 V input
I
3.3 V input
Active
Level
Low
Low
Low
Low
Function
Crystal oscillator in or clock input
Oscillator out
Asynchronous chip reset
External 1.5 kΩ pull-up resistor control
USB’s downstream facing port D+ signal
USB’s downstream facing port D− signal
USB’s upstream facing port D+ signal
USB’s upstream facing port D− signal
Power mode select
Local power monitor
Reference resistor
Port’s over-current status input
Port’s power supply control output
VBUS monitor
External serial ROM clock out
External serial ROM data IO or power
management mode select
External serial ROM input enable
Amber colored LED control output
Green colored LED control output
LED indicator output for downstream port status
Test signal
Test signal
3.3 V VDD
2.5 V VDD
2.5 V VDD for analog circuit
VSS
VSS for analog circuit
VSS for reference resistor. Connect to AVSS.
Remark “5 V tolerant“ means that the buffer is 3 V buffer with 5 V tolerant circuit.
6
Data Sheet S16616EJ2V0DS
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