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UPD720113GK-9EU 查看數據表(PDF) - NEC => Renesas Technology

零件编号
产品描述 (功能)
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UPD720113GK-9EU
NEC
NEC => Renesas Technology NEC
UPD720113GK-9EU Datasheet PDF : 32 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
µPD720113
1. PIN INFORMATION
Pin Name
X1_CLK
X2
SYSRSTB
RPU
DP(7:1)
DM(7:1)
DPU
DMU
LPWRM
RREF
CSB(7:1)
PPB(7:1)
VBUSM
SCL
SDA/GANG_B
EXROM_EN
TEST
SCAN_MODE
VDD33
VDD25
AVDD
VSS
AVSS
AVSS(R)
I/O
Buffer Type
I
O
I
A (O)
I/O
I/O
I/O
I/O
I
A (O)
I
O
I
O
I/O
2.5 V Input
2.5 V Output
5 V tolerant Schmitt Input
USB Pull-up control
USB D+ signal I/O
USB Dsignal I/O
USB D+ signal I/O
USB Dsignal I/O
3.3 V Schmitt Input
Analog
5 V tolerant Input
5 V tolerant N-ch open drain
5 V tolerant Schmitt input
3.3 V Output
3.3 V Schmitt I/O
I
3.3 V Schmitt Input
I
3.3 V Input
I
3.3 V Input
Active
Level
Low
Low
Low
Function
Crystal oscillator in or clock input
Oscillator out
Asynchronous chip reset
External 1.5 kpull-up resistor control
USB’s downstream facing port D+ signal
USB’s downstream facing port Dsignal
USB’s upstream facing port D+ signal
USB’s upstream facing port Dsignal
Local power monitor
Reference resistor
Port’s over-current status input
Port’s power supply control output
VBUS monitor
External serial ROM clock out
External serial ROM data IO or power
management mode select
External serial ROM input enable
Test signal
Test signal
3.3 V VDD
2.5 V VDD
2.5 V VDD for analog circuit
VSS
VSS for analog circuit
VSS for reference resistor. Connect to AVSS.
Remark “5 V tolerant“ means that the buffer is 3 V buffer with 5 V tolerant circuit.
6
Data Sheet S16618EJ3V0DS

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