LT8330 查看數據表（PDF） - Linear Technology

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LT8330

Low IQ Boost/SEPIC/ Inverting Converter with 1A, 60V Switch

Linear Technology 

LT8330

Operation

The LT8330 uses a fixed frequency, current mode control

scheme to provide excellent line and load regulation. Op-

eration can be best understood by referring to the Block

Diagram. An internal 2MHz oscillator turns on the internal

power switch at the beginning of each clock cycle. Current

in the inductor then increases until the current comparator

trips and turns off the power switch. The peak inductor

current at which the switch turns off is controlled by the

voltage on the internal VC node. The error amplifier servos

the VC node by comparing the voltage on the FBX pin with

an internal reference voltage (1.60V or –0.80V, depending

on the chosen topology). When the load current increases

it causes a reduction in the FBX pin voltage relative to

the internal reference. This causes the error amplifier to

increase the VC voltage until the new load current is satis-

fied. In this manner, the error amplifier sets the correct

peak switch current level to keep the output in regulation.

The LT8330 is capable of generating either a positive or

negative output voltage with a single FBX pin. It can be

configured as a boost or SEPIC converter to generate a

positive output voltage, or as an inverting converter to

generate a negative output voltage. When configured as

a boost converter, as shown in the Block Diagram, the

FBX pin is pulled up to the internal bias voltage of 1.60V

by a voltage divider (R1 and R2) connected from VOUT

to GND. Amplifier A2 becomes inactive and amplifier A1

performs (inverting) amplification from FBX to VC. When

the LT8330 is in an inverting configuration, the FBX pin

is pulled down to –0.80V by a voltage divider from VOUT

to GND. Amplifier A1 becomes inactive and amplifier A2

performs (non-inverting) amplification from FBX to VC.

If the EN/UVLO pin voltage is below 1.6V, the LT8330

enters undervoltage lockout (UVLO), and stops switching.

When the EN/UVLO pin voltage is above 1.68V (typical),

the LT8330 resumes switching. If the EN/UVLO pin volt-

age is below 0.2V, the LT8330 only draws 1µA from VIN.

To optimize efficiency at light loads, the LT8330 operates

in Burst Mode operation in light load situations. Between

bursts, all circuitry associated with controlling the output

switch is shut down, reducing the input supply current

to 6µA.

Applications Information

Achieving Ultralow Quiescent Current

To enhance efficiency at light loads the LT8330 uses

a low ripple Burst Mode architecture. This keeps the

output capacitor charged to the desired output voltage

while minimizing the input quiescent current and output

ripple. In Burst Mode operation the LT8330 delivers single

small pulses of current to the output capacitor followed

by sleep periods where the output power is supplied by

the output capacitor. While in sleep mode the LT8330

consumes only 6µA.

the output should also be minimized as they all add to the

equivalent output load. The largest contributor to leakage

current can be due to the reverse biased leakage of the

Schottky diode (see Diode Selection in the Applications

Information section).

2.5

FRONT PAGE APPLICATION

VIN = 12V

2.0

VOUT = 48V

1.5

As the output load decreases, the frequency of single cur-

rent pulses decreases (see Figure 1) and the percentage

of time the LT8330 is in sleep mode increases, resulting

in much higher light load efficiency than for typical con-

verters. To optimize the quiescent current performance

at light loads, the current in the feedback resistor divider

must be minimized as it appears to the output as load

current. In addition, all possible leakage currents from

1.0

0.5

0

0

10

20

30

40

50

LOAD CURRENT (mA)

8330 F01

Figure 1. Burst Frequency vs Load Current

8330fa

8

For more information www.linear.com/LT8330

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