87C196KT 查看數據表（PDF） - Intel
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87C196KT Datasheet PDF : 34 Pages
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87C196KT 87C196KS
CCB (2018H Byte)
0 PD e ‘‘1’’ Enables Powerdown
1 BW0 e See Table
2 WR e ‘‘1’’ e WR BHE - ‘‘0’’ e WRL WRH
3 ALE e ‘‘1’’ e ALE - ‘‘0’’ e ADV
( 4 IRC0 e
5 IRC1 e
See Table
( 6 LOC0 e
7 LOC1 e
See Table
LOC1
0
0
1
1
LOC0
0
1
0
1
Function
Read and Write Protected
Write Protected Only
Read Protected Only
No Protection
MSEL1
0
0
1
1
MSEL0
0
1
0
1
Bus Timing Mode
Mode 0 (1-Wait KR)
Mode 1
Mode 2
Mode 3 (KR)
Mode 0
Designed to be similar to the 87C196KR bus
(1-Wait KR) timing with 1 automatic wait state
See AC Timings section for actual timings data
Mode 1
Mode 2
Mode 3 (KR)
RD WR advanced 1 TOSC
ALE advanced 0 5 TOSC
ALE pulse width remains 1 TOSC
RD WR advanced 1 TOSC
ALE advanced 0 5 TOSC
ALE pulse width remains 1 TOSC
Address advanced 0 5 TOSC
Designed to be similar to the 87C196KR bus
timing
See AC Timings section for actual timings data
CCB1 (201AH Byte)
0
0
e Reserved Must Be ‘‘0’’
1 IRC2 e See Table
2 BW1 e See Table
3 WDE e ‘‘0’’ e Always Enabled
4
5
1
0
e
( Reserved Must Be ‘‘01’’
e
( 6 MSEL0 e
7 MSEL1 e
See Table
IRC2
0
1
1
1
1
IRC1
0
0
0
1
1
IRC0
0
0
1
0
1
Max Wait States
Zero Wait States
1 Wait State
2 Wait States
3 Wait States
INFINITE
BW1
0
0
1
1
BW0
0
1
0
1
Bus Width
ILLEGAL
16-Bit Only
8-Bit Only
BW Pin Controlled
6
6
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