M24M01-VLA6TP 查看數據表（PDF） - STMicroelectronics
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M24M01-VLA6TP Datasheet PDF : 21 Pages
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M24M01
Figure 6. Write Mode Sequences with WC=1 (data write inhibited)
WC
BYTE WRITE
ACK
ACK
ACK
NO ACK
DEV SEL
BYTE ADDR BYTE ADDR
DATA IN
R/W
WC
PAGE WRITE
WC (cont'd)
PAGE WRITE
(cont'd)
ACK
ACK
ACK
NO ACK
DEV SEL
BYTE ADDR BYTE ADDR DATA IN 1
DATA IN 2
R/W
NO ACK
NO ACK
DATA IN N
AI01120C
Write Operations
Following a Start condition the bus master sends
a Device Select Code with the RW bit reset to 0.
The device acknowledges this, as shown in Figure
7, and waits for two address bytes. The device re-
sponds to each address byte with an acknowledge
bit, and then waits for the data byte.
Writing to the memory may be inhibited if Write
Control (WC) is driven High. Any Write instruction
with Write Control (WC) driven High (during a pe-
riod of time from the Start condition until the end of
the two address bytes) will not modify the memory
contents, and the accompanying data bytes are
not acknowledged, as shown in Figure 6.
Each data byte in the memory has a 17-bit ad-
dress. The most significant bit, A16, is sent with
the Device Select Code, and the remaining bits,
A15-A0, in the two address bytes. The Most Sig-
nificant Byte is sent first, followed by the Least Sig-
nificant Byte. Bits A16 to A0 form the address of
the byte in memory.
When the bus master generates a Stop condition
immediately after the Ack bit (in the “10th bit” time
slot), either at the end of a Byte Write or a Page
Write, the internal memory Write cycle is triggered.
A Stop condition at any other time slot does not
trigger the internal Write cycle.
After the Stop condition, the delay tW, and the suc-
cessful completion of a Write operation, the de-
vice’s internal address counter is incremented
automatically, to point to the next byte address af-
ter the last one that was modified.
During the internal Write cycle, Serial Data (SDA)
is disabled internally, and the device does not re-
spond to any requests.
Byte Write
After the Device Select code and the address
bytes, the bus master sends one data byte. If the
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