P50N03LDG 查看數據表（PDF） - Niko Semiconductor

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P50N03LDG

N-Channel Logic Level Enhancement Mode Field Effect Transistor

Niko Semiconductor 

NIKO-SEM

N-Channel Logic Level Enhancement

Mode Field Effect Transistor

P50N03LDG

TO-252 (DPAK)

Lead-Free

On-State Drain Current1

Drain-Source On-State

Resistance1

Forward Transconductance1

ID(ON)

RDS(ON)

gfs

VDS = 10V, VGS = 10V

VGS = 4.5V, ID = 20A

VGS = 10V, ID = 25A

VDS = 10V, ID = 25A

50

15

10

32

A

18

mΩ

12

S

DYNAMIC

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

Total Gate Charge2

Gate-Source Charge2

Gate-Drain Charge2

Turn-On Delay Time2

Rise Time2

Turn-Off Delay Time2

Fall Time2

Ciss

Coss

Crss

Qg

Qgs

Qgd

td(on)

tr

td(off)

tf

VGS = 0V, VDS = 15V, f = 1MHz

VDS = 10V, VGS = 10V,

ID = 25A

VDS = 15V, RL = 1Ω

ID ≅ 50A, VGS = 10V, RGEN = 24Ω

1200 1800

600 1000 pF

350 500

25 50

15

nC

10

6 16

120 250

nS

40 90

105 200

SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C)

Continuous Current

Pulsed Current3

Forward Voltage1

IS

ISM

VSD

IS = 25A, VGS = 0V

50

A

150

0.9 1.3 V

Reverse Recovery Time

trr

70

nS

Peak Reverse Recovery Current

IRM(REC)

IF = IS, dlF/dt = 100A / µS

200

A

Reverse Recovery Charge

Qrr

1Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2％.

2Independent of operating temperature.

3Pulse width limited by maximum junction temperature.

0.043

µC

REMARK: THE PRODUCT MARKED WITH “P50N03LDG”, DATE CODE or LOT #

Orders for parts with Lead-Free plating can be placed using the PXXXXXXXG parts name.

2

SEP-22-2004

Free Datasheet http://www.datasheet-pdf.com/

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