AS7C3256A-12TC 查看數據表（PDF） - Alliance Semiconductor
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AS7C3256A-12TC Datasheet PDF : 9 Pages
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AS7C3256A
®
Functional description
The AS7C3256A is a 3.3V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device
organized as 32,768 words × 8 bits. It is designed for memory applications requiring fast data access at low voltage,
including PentiumTM, PowerPCTM, and portable computing. Alliance’s advanced circuit design and process techniques
permit 3.3V operation without sacrificing performance or operating margins.
The device enters standby mode when CE is high. CMOS standby mode consumes 7.2 mW. Normal operation offers 75%
power reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns
are ideal for high-performance applications. The chip enable (CE) input permits easy memory expansion with multiple-bank
memory organizations.
A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7
is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should
drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) high. The
chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write
enable is low, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible. Operation is from a single 3.3 ±0.3V supply. The AS7C3256A is packaged
in high volume industry standard packages.
Absolute maximum ratings
Parameter
Symbol
Min
Voltage on VCC relative to GND
Vt1
–0.5
Voltage on any pin relative to GND
Vt2
–0.5
Power dissipation
PD
–
Storage temperature (plastic)
Tstg
–65
Ambient temperature with VCC applied
Tbias
–55
DC current into outputs (low)
IOUT
–
Max
Unit
+5.0
V
VCC + 0.5
V
1.0
W
+150
oC
+125
oC
20
mA
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
WE
H
X
L
H
L
H
L
L
Key: X = Don’t care, L = Low, H = High
OE
Data
X
High Z
H
High Z
L
DOUT
X
DIN
Mode
Standby (ISB, ISB1)
Output disable (ICC)
Read (ICC)
Write (ICC)
4/23/04; v.2.0
Alliance Semiconductor
P. 2 of 9
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