AS7C3256A-10JI 查看數據表（PDF） - Alliance Semiconductor
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AS7C3256A-10JI Datasheet PDF : 9 Pages
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AS7C3256A
®
Read cycle (over the operating range)3,9
-10
Parameter
Symbol Min Max
Read cycle time
tRC
10 –
Address access time
tAA
– 10
Chip enable (CE) access time
tACE
– 10
Output enable (OE) access time tOE
–
5
Output hold from address change tOH
CE LOW to output in low Z
tCLZ
3
–
3
–
CE HIGH to output in high Z
tCHZ
–
3
OE LOW to output in low Z
tOLZ
0
–
OE HIGH to output in high Z
tOHZ
–
3
Power up time
Power down time
tPU
0
–
tPD
– 10
-12
Min Max
12 –
– 12
– 12
–
6
3
–
3
–
–
3
0
–
–
3
0
–
– 12
-15
Min Max
15 –
– 15
– 15
–
7
3
–
3
–
–
4
0
–
–
4
0
–
– 15
-20
Min Max
20 –
– 20
– 20
–
8
3
–
3
–
–
5
0
–
–
5
0
–
– 20
Unit Notes
ns
ns 3
ns 3
ns
ns 5
ns 4, 5
ns 4, 5
ns 4, 5
ns 4, 5
ns 4, 5
ns 4, 5
Key to switching waveforms
Rising input
Falling input
Undefined output/don’t care
Read waveform 1 (address controlled)3,6,7,9
tRC
Address
tAA
tOH
Dout
Data valid
Read waveform 2 (CE controlled)3,6,8,9
tRC1
CE
tOE
OE
tOLZ
tOHZ
tACE
tCHZ
Dout
Data valid
Supply
current
tCLZ
tPU
50%
tPD
ICC
50%
ISB
4/23/04; v.2.0
Alliance Semiconductor
P. 4 of 9
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