AS7C3256A-12TC 查看數據表（PDF） - Alliance Semiconductor

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AS7C3256A-12TC

3.3V 32K X 8 CMOS SRAM (Common I/O)

Alliance Semiconductor 

AS7C3256A

®

Write cycle (over the operating range)11

-10

Parameter

Symbol Min Max

Write cycle time

tWC

10

–

Chip enable to write end

tCW

8

–

Address setup to write end

tAW

8

–

Address setup time

tAS

0

–

Write pulse width

tWP

7

–

Write recovery time

tWR

0

–

Address hold from end of write

tAH

0

–

Data valid to write end

tDW

5

–

Data hold time

tDH

0

–

Write enable to output in high Z tWZ

–

5

Output active from write end

tOW

3

–

-12

Min Max

12 –

8

–

8

–

0

–

8

–

0

–

0

–

6

–

0

–

–

6

3

–

-15

Min Max

15 –

10 –

10 –

0

–

9

–

0

–

0

–

8

–

0

–

–

7

3

–

-20

Min Max

20 –

12 –

12 –

0

–

12 –

0

–

0

–

10 –

0

–

–

8

3

–

Unit Notes

ns

ns

ns

ns

ns

ns

ns

ns

ns 4, 5

ns 4, 5

ns 4, 5

Write waveform 1 (WE controlled)10,11

Address

tWC

tAW

tWP

WE

tAS

Din

tWZ

Dout

tAH

tWR

tDW

tDH

Data valid

tOW

Write waveform 2 (CE controlled)10,11

tWC

tAW

tAH

Address

CE

WE

Din

Dout

tAS

tCW

tWR

tWP

tWZ

tDW

tDH

Data valid

4/23/04; v.2.0

Alliance Semiconductor

P. 5 of 9

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