UJA1075ATW/5V0 查看數據表（PDF） - NXP Semiconductors.
零件编号
产品描述 (功能)
生产厂家
UJA1075ATW/5V0 Datasheet PDF : 54 Pages
| |||
NXP Semiconductors
UJA1075A
High-speed CAN/LIN core system basis chip
from Standby or Normal
VBAT below
power-off threshold Vth(det)poff
(from all modes)
Overtemp
V1: OFF
V2: OFF
limp home = LOW (active)
CAN/LIN: Off and
high resistance
watchdog: OFF
chip temperature above
OTP activation threshold Tth(act)otp
VBAT below
power-on threshold Vth(det)pon
Off
V1: OFF
V2: OFF
CAN/LIN: Off and
high resistance
watchdog: OFF
INTN: HIGH
chip temperature below
OTP release threshold Tth(rel)otp
VBAT above
power-on threshold Vth(det)pon
watchdog overflow or
V1 undervoltage
Standby
watchdog
trigger
V1: ON
V2: OFF
CAN/LIN: Lowpower/Off
watchdog: Timeout/Off
MC = 00
reset event or
MC = 00
MC = 10 or MC = 11
MC = 01 and
INTN = HIGH and
one wake-up enabled and
no wake-up pending
successful
watchdog
trigger
Normal
V1: ON
V2: ON/OFF
CAN/LIN: Active/Lowpower
watchdog: Window/
Timeout/Off
MC = 1x
Fig 3. UJA1075A system controller
wake-up event if enabled
MC = 01 and
INTN = HIGH and
one wake-up enabled and
no wake-up pending
Sleep
V1: OFF
V2: OFF
CAN/LIN: Lowpower/Off
watchdog: OFF
RSTN: LOW
MC = 01
015aaa073
UJA1075A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 28 January 2011
© NXP B.V. 2011. All rights reserved.
8 of 54
Share Link: 