QL8X12B-0PF100C 查看數據表（PDF） - QuickLogic Corporation

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QL8X12B-0PF100C

pASIC 1 Family Very-High-Speed CMOS FPGA

QuickLogic Corporation 

QL8X12B

High Drive Buffer

Symbol

Parameter

tIN

High Drive Input Delay

tINI

High Drive Input,

Inverting Delay

Clock Drivers

Wired Together

1

2

3

4

1

2

3

4

Propagation Delays (ns) [4]

Fanout

12 24 48 72 96

4.0 4.9

3.5 5.0

4.0 4.8 5.6

4.1 4.8

4.2 5.1

3.7 5.2

4.2 5.0 5.8

4.3 5.0

AC Performance

Propagation delays depend on routing, fanout, load capacitance, supply voltage, junction temperature,

and process variation. The AC Characteristics are a design guide to provide initial timing estimates at

4

nominal conditions. Worst case estimates are obtained when nominal propagation delays are multiplied

by the appropriate Delay Factor, K, as specified in the Delay Factor table (Operating Range). The

effects of voltage and temperature variation are illustrated in the graphs on page 4-47, K Factor versus

Voltage and Temperature. The pASIC Development Tools incorporate data sheet AC Characteristics

into the QDIF database for pre-place-and-route timing analysis. The SpDE Delay Modeler extracts

specific timing parameters for precise path analysis or simulation results following place and route.

ORDERING

INFORMATION

QuickLogic

pASIC device

pASIC device part number

B = 0.65 micron CMOS

Speed Grade

X = quick

0 = fast

1 = faster

2 = fastest

QL 8x12B - 1 PL68 C

4-11

Operating Range

C = Commercial

I = Industrial

M = Military

Package Code

PL44 = 44-pin PLCC

PL68 = 68-pin PLCC

PF100 = 100-pin TQFP

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