ICS853111-01 查看數據表（PDF） - Integrated Device Technology

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ICS853111-01

LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER

Integrated Device Technology 

ICS853111-01

LOW SKEW, 1-TO-9

DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER

POWER CONSIDERATIONS

This section provides information on power dissipation and junction temperature for the ICS853111-01.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS853111-01 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for V = 3.8V, which gives worst case results.

CC

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

• Power (core) = V

*I

= 3.8V * 75mA = 285mW

MAX

CC_MAX EE_MAX

• Power (outputs)MAX = 30.94mW/Loaded Output pair

If all outputs are loaded, the total power is 9 * 30.94mW = 278.5mW

Total Power_MAX (3.8V, with all outputs switching) = 285mW + 278.5mW = 563.5mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the

device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.

The equation for Tj is as follows: Tj = θJA * Pd_total + TA

Tj = Junction Temperature

θJA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a

moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 31.1°C/W per Table 5 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.564W * 31.1°C/W = 102°C. This is well below the limit of 125°C.

This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,

and the type of board (single layer or multi-layer).

TABLE 5. THERMAL RESISTANCE θJA FOR 28-PIN PLCC, FORCED CONVECTION

θ by Velocity (Linear Feet per Minute)

JA

Multi-Layer PCB, JEDEC Standard Test Boards

0

37.8°C/W

200

31.1°C/W

500

28.3°C/W

NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.

853111AV-01

10

REV. A NOVEMBER 14, 2007

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