FM24C16A 查看數據表（PDF） - Ramtron International Corporation

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FM24C16A

16Kb FRAM Serial Memory

Ramtron International Corporation 

FM24C16A

Diagram Notes

All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read

and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional

relationships are illustrated in the relevant data sheet sections. These diagrams illustrate the timing parameters only.

Read Bus Timing

tR

t HIGH

tF

t LOW

t SP

t SP

SCL

SDA

t SU:SDA

t BUF

1/fSCL

t HD:DAT

t SU:DAT

Start

Stop Start

t AA

t DH

Acknowledge

Write Bus Timing

SCL

SDA

t SU:STO

t HD:DAT

t HD:STA

t SU:DAT

Start

Stop Start

t AA

Acknowledge

Data Retention (VDD = 4.5V to 5.5V, +85° C)

Parameter

Min

Data Retention

45

Units

Years

Notes

Rev 3.0

Mar. 2005

Page 10 of 12

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