AS2701 查看數據表（PDF） - austriamicrosystems AG

零件编号

产品描述 (功能)

生产厂家

AS2701

AS-Interface Slave IC

austriamicrosystems AG 

AS-Interface Slave IC

AS2701A (ISA3+)

Write Cycle

After the device address, the write cycle R/W-Bit=0, necessary for the identification of the write

cycle, is sent. The E2PROM acknowledges the correct receipt with the acknowledge bit ACK.

Then the data byte which should be written into the E2PROM reacknowledges with an ACK

signal of the E2PROM. The STOP condition ends the cycle.

Read Cycle

The read cycle is similar to the herein described write cycle. In this case the R/W-Bit = 1 which

causes the E2PROM to place read data for the received Byte address on the bus after the

acknowledge.

SDA

SCL

START

Condition

STOP

Condition

The START condition is recognized by the E2PROM when a H/L edge arises on the dataline

SDA during the high phase of the clock.

The STOP condition is present when a L/H edge arises on the dataline SDA during the high

phase of the clock SCL. The timing of the E2PROM interface is derived from the AS-Interface

quartz frequency of 5.333 MHz.

Rev. C, October 2000

Page 5 of 16

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