AS1746-BWLT 查看數據表（PDF） - austriamicrosystems AG
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AS1746-BWLT Datasheet PDF : 15 Pages
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AS1746
Datasheet - Application Information
Test Circuits and Timing Diagrams
Figure 17. Switching Time
V+
VIN
NOx or NCx
INx
Logic
Input
AS1746
COMx
RLOAD
50Ω
VOUT
CLOAD †
35pF
VIH
Logic
Input
VIL
VOUT
Switch
Output 0
GND
( ) VOUT = VNx
RLOAD
RLOAD + RON
† Includes stray capacitance and fixture capacitance.
50%
50%
tR < 5ns
tF < 5ns
tOFF
0.9 x VOUT
0.9 x VOUT
tON
Logic input waveforms inverted for switches
that have the opposite logic sense.
Figure 18. Break-Before-Make Interval
V+ AS1746
VIN
NCx
COMx
VOUT
NOx
RLOAD
50Ω
CLOAD †
35pF
INx
VIH
Logic
Input
0
VOUT
50%
Logic
Input
GND
tD
† Includes stray capacitance and fixture capacitance.
0.9 x VOUT
Figure 19. Charge Injection
V+
INx
VIL to
VIH
COMx
RGEN
AS1746
VGEN
GND
NOx or NCx
VOUT
CLOAD
VOUT
ΔVOUT
INx Off
On
Off
INx
Off
On
Off
Q = ΔVOUT x CLOAD
INx depends on switch configuration; input polarity is determined
by the sense of the switches.
www.austriamicrosystems.com
Revision 1.03
10 - 15
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