AS3843N13 查看數據表（PDF） - Astec Semiconductor => Silicon Link

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AS3843N13

Current Mode Controller

Astec Semiconductor => Silicon Link 

Current Mode Controller

AS384x

In most typical power supply designs, the con-

verterÕs output voltage is divided down and moni-

tored at the error amplifierÕs inverting input, VFB. A

simple resistor divider network is used and is

scaled such that the voltage at VFB is 2.5 V when

the converterÕs output is at the desired voltage.

The voltage at VFB is then compared to the inter-

nal 2.5 V reference and any slight difference is

amplified by the high gain of the error amplifier.

The resulting error amplifier output is level shifted

by two diode drops and is then divided by three to

provide a 0 to 1 V reference (VE) to one input of

the current sense comparator. The level shifting

reduces the input voltage range of the current

sense input and prevents the output from going

high when the error amplifier output is forced to its

low state. An internal clamp limits VE to 1.0 V. The

purpose of the clamp is discussed in Section 1.5.

1.4.1 Loop compensation

Loop compensation of a power supply is neces-

sary to ensure stability and provide good line/load

regulation and dynamic response. It is normally

provided by a compensation network connected

between the error amplifierÕs output (COMP) and

inverting input as shown in Figure 17. The type of

network used depends on the converter topology

and in particular, the characteristics of the major

functional blocks within the supply Ñ i.e. the error

amplifier, the modulator/switching circuit, and the

output filter. In general, the network is designed

such that the converterÕs overall gain/phase

response approaches that of a single pole with a

Ð20 dB/decade rolloff, crossing unity gain at the

highest possible frequency (up to fSW/4) for good

dynamic response, with adequate phase margin

(> 45¡) to ensure stability.

Figure 18 shows the Gain/Phase response of the

error amplifier. The unity gain crossing is at

1.2 MHz with approximately 57¡C of phase mar-

gin. This information is useful in determining the

configuration and characteristics required for the

compensation network.

One of the simplest types of compensation net-

works is shown in Figure 19. An RC network pro-

vides a single pole which is normally set to

compensate for the zero introduced by the output

capacitorÕs ESR. The frequency of the pole (fP) is

determined by the formula;

1

ƒP = 2π Rƒ Cƒ

(5)

80

240

210

Gain

60

180

Phase

150

40

120

90

20

60

30

0

0

–30

–20

–60

101

102

103 104

105

106 107

Frequency (Hz)

Figure 18. Gain/Phase Response of the AS3842

VOUT

RI

RBIAS

CF

RF

Ð

E/A

+

2.50 V

To PWM

Figure 19. A Typical Compensation Network

ASTEC Semiconductor

15

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