LE28FV4001T-20 查看數據表（PDF） - SANYO -> Panasonic
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LE28FV4001T-20 Datasheet PDF : 14 Pages
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LE28FV4001M, T, R-20/25
2. Software data protection
As mentioned earlier, the LE28FV4001 Series is designed to provide even more protection from unintentional writes
in software. To avoid unintentional erasure or programming of sector or device cells, when the application system
attempts to execute a sector erase or programming operation it must execute that operation as a two-stage sequence
consisting of first of a setup command and then an execute command.
As a default, the LE28FV4001 Series products go to the write protected state after power is applied. The device goes
to the unprotected state after reads to seven specific addresses are executed consecutively. Those addresses are
1823H, 1820H, 1822H, 0418H, 041BH, 0419H, and 041AH. The address is latched on the rise of either OE or CE,
whichever is earlier. Similarly, the device can be set to the write protect state by reading from the following 7
addresses consecutively: 1823H, 1820H, 1822H, 0418H, 041BH, 0419H, and 040AH. Figures 9 and 10 show the
software data protection waveforms for these 7-read-cycle sequences. The I/O pins can go to any state (high, low, or
high impedance).
Detection of Write Operation Completion
To acquire the maximum performance from the device, applications must detect the completion of the programming
cycle. The completion of the programming cycle can be detected by either Data polling or the toggle bit. This section
describes these two detection mechanisms.
Actually, the completion of a nonvolatile memory write operation is asynchronous with respect to the application
system. Therefore, it is possible that readout of either Data polling or toggle bit data could occur at the same time as the
completion of the write cycle. If this happens the application system could receive an incorrect result. That is, valid data
could appear to contradict either DQ7 or DQ6. To prevent false negatives, if an incorrect result occurs the software
routine must include a loop to read the accessed location another 2 times. If both these readout cycles acquire valid data
the device will have completed the write cycle. All other reject states are correct.
1. Data polling (DQ7)
The LE28FV4001M, LE28FV4001T, and LE28FV4001R products provide a Data polling function that detects the
completion of the programming cycle. During the program cycle, DQ7 reads out Data that is the negation of the most
recently loaded data. When the programming cycle has complete, DQ7, along with DQ0 to DQ6, reads out the last
loaded data. Figure 11 shows the timing chart for this operation. For data polling to function correctly, data must be
erased before programming.
2. Toggle bit (DQ6)
The DQ6 toggle bit is another technique for detecting the end of the erase or programming cycle. During an erase or
programming operation the value of the DQ6 output alternates between 0 and 1, that is, the DQ6 output toggles
between 0 and 1. When the erase or programming cycle completes, the toggling stops and the device goes to a
normal read cycle. The toggle bit can be continuously monitored during an erase or programming cycle. Figure 12
shows the timing chart for toggle bit operation.
3. Continuous read
One more technique for detecting the end of an erase or programming cycle is to read the same address twice in a
row. If the same data is read twice in a row the erase or programming cycle has completed.
Product Identifier
Product identifier read is a mode provided so that applications can confirm that the device was manufactured by Sanyo
Electric Co., Ltd. This mode can be accessed by both hardware and software operations. A ROM writer is normally used
with this hardware operation to recognize the correct algorithm for these products. We recommend that users use the
software operation for recognizing this device. The “Functional Logic” section describes the hardware operation in
detail. The manufacturer and device code are accessed in the same manner.
Decoupling Capacitors
A 0.1-µF ceramic capacitors must be inserted between VDD and VSS for each device to assure stabile flash memory
operation.
No. 5468-6/14
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