FMP1617CA5 查看數據表（PDF） - FIDELIX

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FMP1617CA5

1M x 16 bit Super Low Power and Low Voltage Full CMOS RAM

FIDELIX 

FMP1617CAx

CMOS LPRAM

PAGE WRITE CYCLE (Address controlled, /ZZ=VIH)

A0~A3

tMRC

tWC

tPC

tPC

tPC

tPC

tPC

tPC

tPC

A4~A20

/CS

/UB, /LB

/WE

tAS(3)

Data in

Data Out

High-Z

tWHZ

Data Undefined

tDW tDH tDW tDH tDW tDH tDW tDH tDW tDH tDW tDH tDW tDH tDW tDH

Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid

High-Z

tOW

1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with

asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write

ends at the earliest transition when /CS goes high and /WE goes high. The tWP is measured from the beginning of write to

the end of write.

2. tCW is measured from the /CS going low to end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high.

5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us.

6. In case page address is over 3ns, write to the invalid address can occur.

9

Revision 0.1

Jun. 2006

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