QL5632-BPQ208C 查看數據表（PDF） - QuickLogic Corporation

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QL5632-BPQ208C

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

QuickLogic Corporation 

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[9:0]

[17:0]

[1:0]

WA

RE

WD

WE

WCL K

MOD E

RCLK

[9:0]

RA

[17:0]

RD

ASYNCRD

QuickRAM Module

Figure 4: RAM Module

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Traditional Programmable Logic architectures do not implement arithmetic functions

efficiently or effectively—these functions require high logic cell usage while garnering only

moderate performance results.

The QL5632 architecture allows for functionality above and beyond that achievable using

programmable logic devices. By embedding a dynamically reconfigurable computational unit,

the QL5632 device can address various arithmetic functions efficiently. This approach offers

greater performance than traditional programmable logic implementations. The embedded

block is implemented at the transistor level as shown in )LJXUH .

RESET

S1

S2

S3

CIN

SIGN1

SIGN2

A[0:7]

A[8:15]

D

C

3-4

decoder

B

A

8-bit

2-1

Multiplier

mux

16-bit

Adder

DQ

17 inc. 17-bit

COUT Register

00

01

3-1

mux

10

Q[0:16]

A[0:15]

CLK

B[0:15]

2-1

mux

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Figure 5: ECU Block Diagram

Preliminary

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