LCX032AKB
2. Clock timing conditions (Ta = 25°C, Input voltage = 3.0V, VDD = 12.0V)
Item
Hst rise time
Hst fall time
HST
Hst data set-up time
HCK
Hst data hold time
Hckn∗2 rise time
Hckn∗2 fall time
Hck1 fall to Hck2 rise time
Hck1 rise to Hck2 fall time
Vst rise time
Vst fall time
VST
Vst data set-up time
Vst data hold time
Vck rise time
VCK
Vck fall time
En rise time
En fall time
EN
Vck fall to En fall time
Vck rise to En rise time
BLK rise time
BLK∗3 BLK fall time
BLK pulse width
BLK fall to CLR fall time
Symbol
trHst
tfHst
tdHst
thHst
trHckn
tfHckn
to1Hck
to2Hck
trVst
tfVst
tdVst
thVst
trVck
tfVck
trEn
tfEn
tdVck2
tdVck1
trBlk
tfBlk
twBlk
toClr
Min.
–170
–455
–15
–15
–50
–50
–100
–100
600
∗2 Hckn means Hck1, Hck2. (fHckn = 1.84MHz, fVckn = 7.865kHz)
∗3 BLK pulse is used only for 16:9 mode. For 4:3 mode, connect to VSS.
Typ.
135
–135
0
0
32
–32
0
0
1.0
700
Max. Unit
30
30
170
–50
30
ns
30
15
15
100
100
50
µs
–20
100
100
100
100
ns
100
100
100
100
ms
800
ns
–7–