M5M5V208AKV-70L 查看數據表（PDF） - MITSUBISHI ELECTRIC
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M5M5V208AKV-70L Datasheet PDF : 8 Pages
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Revision-A0.2E 29.Jan.'99
M5M5V208AKV/KR
MITSUBISHI LSIs
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS
( Vcc= 2.7 ~ 3.6V, unless otherwise noted)
(1) MEASUREMENT CONDITIONS
Vcc
................................. 2.7 ~ 3.6V
Input pulse level ............. VIH=2.2V,VIL=0.4V
Input rise and fall time ..... 5ns
Reference level ............... VOH=VOL=1.5V
Output loads ................... Fig.1,CL=30pF
CL=5pF (for ten,tdis)
Transition is measured ±500mV from steady
state voltage. (for ten,tdis)
1TTL
DQ
CL
including
scope and JIG
Fig.1 Output load
(2) READ CYCLE
Symbol
Parameter
tCR
ta(A)
ta(S1)
ta(S2)
ta(OE)
tdis(S1)
tdis(S2)
tdis(OE)
ten(S1)
ten(S2)
ten(OE)
tV(A)
Read cycle time
Address access time
Chip select 1 access time
Chip select 2 access time
Output enable access time
Output disable time after S1 high
Output disable time after S2 low
Output disable time after OE high
Output enable time after S1 low
Output enable time after S2 high
Output enable time after OE low
Data valid time after address
Limits
-55L,H
Min Max
-70L,H
Min Max
Unit
55
70
ns
55
70 ns
55
70 ns
55
70 ns
30
35 ns
20
25 ns
20
25 ns
20
25 ns
10
10
ns
10
10
ns
5
5
ns
10
10
ns
(3) WRITE CYCLE
Limits
Symbol
Parameter
-55L,H -55L,H Unit
Min Max Min Max
tCW
Write cycle time
55
70
ns
tw(W) Write pulse width
45
55
ns
tsu(A) Address setup time
0
0
ns
tsu(A-WH) Address setup time with respect to W 50
65
ns
tsu(S1) Chip select 1 setup time
50
65
ns
tsu(S2) Chip select 2 setup time
50
65
ns
tsu(D) Data setup time
25
30
ns
th(D)
Data hold time
0
0
ns
trec(W) Write recovery time
0
0
ns
tdis(W) Output disable time from W low
20
25 ns
tdis(OE) Output disable time from OE high
20
25 ns
ten(W) Output enable time from W high
5
5
ns
ten(OE) Output enable time from OE low
5
5
ns
MITSUBISHI ELECTRIC
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